19.2.4 General Parallel and Multi-Processor Algorithms

Narasimhan, R.,
Some Further Experiments in the Parallel Processing of Pictures,
TC(13), No. 6, 1964, pp. 748-750. BibRef 6400

Kruse, B.[Bjorn],
A Parallel Picture Processing Machine,
TC(22), 1973, pp. 1075-1087. BibRef 7300

Kruse, B.[Bjorn],
Design and Implementation of a Picture Processor,
(with other papers), Linkoping Studies in Science and Technology, Ph.D.Thesis (EE), TR 13, Dept. of EE, 1977, BibRef 7700 Linkoping Univ.S-581, 83, Linkoping, Sweden, 1977. Picture processor (hardware); mini PICAP. TV input, 4 cameras, 64X64 at any position or scale, 3X3 neighborhood or 9 image registers for input to functions. BibRef

Haralick, R.M.[Robert M.], Currier, P.[Phil],
Image Discrimination Enhancement Combination System (IDECS),
CGIP(6), No. 4, August 1977, pp. 371-381.
WWW Version. System: IDECS. Describes their hardware system. Operates at video rates, TV size, data disk storage, input/output connected by a switch, with digital and analog processors. BibRef 7708

Klette, R.,
Parallel Operations on binary Images,
CGIP(14), No. 2, October 1980, pp. 145-158.
WWW Version. BibRef 8010

Reeves, A.P.,
An array processing system with a Fortran-based realization,
CGIP(9), No. 3, March 1979, pp. 267-281.
WWW Version. 0501
BibRef

Reeves, A.P.,
On Efficient Global Information Extraction Methods for Parallel Processors,
CGIP(14), No. 2, October 1980, pp. 159-169.
WWW Version. BibRef 8010

Otto, G.P., Reynolds, D.E.,
Note on Bit Counting hardware for parallel processors,
CGIP(17), No. 2, October 1981, pp. 185-186.
WWW Version. 0501
BibRef

Reeves, A.P.,
Response to 'A note on bit-counting hardware for parallel processors',
CGIP(17), No. 2, October 1981, pp. 187-188.
WWW Version. 0501
BibRef

Siegel, L.J., Siegel, H.J., Feather, A.E.,
Parallel Processing Approaches to Image Correlation,
TC(31), 1982, pp. 208-218. BibRef 8200

Rosenfeld, A.[Azriel], Wu, A.Y.[Angela Y.],
Parallel computers for region-level image processing,
PR(15), No. 1, 1982, pp. 41-50.
WWW Version. 0309
BibRef

Wu, A.Y.,
Parallel Image Processing,
FIU01(Chapter 6). BibRef 0100

Engbersen, A.P.J.[Antonius Paulus Johannes],
TOPPSY: A Time Overlapped Parallel Processing System,
CVGIP(24), No. 1, October 1983, pp. 97-106.
WWW Version. From IBM Zurich. Software interface to a parallel processor machine. The number of processors is used to speed up the processing of window type operations. There has been extensive work to develop transparent software to make it easier to use. BibRef 8310

Basille, J.L., Castan, S., Al Rozz, M.,
Parallel Architectures Adapted to Image Processing and Their Limits,
CSIP83(31-42). BibRef 8300

Franchi, P., Gonzalez, J., Mantey, P., Paoli, C., Parolo, A., Simmons, J.,
Design Issues and Architecture of HACIENDA, an Experimental Image Processing System,
IBMRD(27), No. 2, March, 1983, pp. 116-126. BibRef 8303

Kushner, T.R.[Todd R.], Rosenfeld, A.[Azriel],
A Model of Interprocessor Communication for Parallel Image Processing,
SMC(13), 1983, pp. 600-618. BibRef 8300

Yalamanchili, S., Aggarwal, J.K.,
Analysis of a Model for Parallel Image Processing,
PR(18), No. 1, 1985, pp. 1-16.
WWW Version. BibRef 8500
And:
Parallel Image Processing with the Shuffle Exchange Network,
CVWS84(31-36). BibRef

Yalamanchili, S., Aggarwal, J.K.,
A System Organization for Parallel Image Processing,
PR(18), No. 1, 1985, pp. 17-29.
WWW Version. BibRef 8500

Yalamanchili, S., Aggarwal, J.K.,
Formulation of Parallel Image Processing Tasks,
PRL(2), 1984, pp. 261-270. BibRef 8400

Hwang, K.,
Advanced Parallel Processing with Supercomputer Architectures,
PIEEE(75), 1987, pp. 1348-1379. BibRef 8700

Chang, S.K., Tauber, M.J., Yu, B., Yu, J.S.,
The Sil-Icon Compiler: An Icon-Oriented System Generator,
PRAI(2), 1988, pp. 241-273. BibRef 8800

Paul, D., Hattich, W., Nill, W., Tatari, S., and Winkler,G.,
VISTA: Visual Interpretation System for Technical Applications - Architecture and Use,
PAMI(10), No. 3, May 1988, pp. 399-407.
IEEE Abstract. IEEE Top Reference.
WWW Version. BibRef 8805

Schmitt, L.A., and Wilson, S.S.,
The AIS-5000 Parallel Processor,
PAMI(10), No. 3, May 1988, pp. 320-330.
IEEE Abstract. IEEE Top Reference.
WWW Version. BibRef 8805

Maresca, M., Lavin, M.A., and Li , H.,
Parallel Architectures for Vision,
PIEEE(76), No. 8, August 1988, pp. 970-981. BibRef 8808

Stout, Q.F.[Quentin F.],
Mapping Vision Algorithms to Parallel Architectures,
PIEEE(76), No. 8, August 1988, pp. 982-995. BibRef 8808

Choudhary, A.N., and Patel, J.H.,
Parallel Architectures and Parallel Algorithms for Integrated Vision Systems,
Hingham, MA: KluwerAcademic, September 1990. ISBN 0-7923-9078-4. Techniques to map vision algorithms to parallel systems.
WWW Version. BibRef 9009

Reinhart, C.C.,
Specifying Parallel Processor Architectures for High-Level Computer Vision Algorithms,
Ph.D.Thesis (EE-CE), October 1981, BibRef 8110 USC_IRIS-TR-284. BibRef

Nevatia, R., Reinhart, C.C.,
Parallel Processing for Spatial Grouping and Matching,
ICPR94(C:290-294).
IEEE DOI Link BibRef 9400 USC Computer Vision BibRef

Reinhart, C.C., and Nevatia, R.,
Parallel Linear Feature Extraction,
DARPA92(1049-1055). BibRef 9200 USC Computer Vision BibRef
Earlier:
Efficient Parallel Processing in High Level Vision,
DARPA90(829-839). Study various algorithms for implementation on different processors. BibRef

Reinhart, C.C., Nevatia, R.,
Issues In Parallel Tree Search for Object Recognition,
ICPR92(IV:225-228).
IEEE DOI Link BibRef 9200 USC Computer Vision BibRef

Fairhurst, M.C., Abdel Wahab, H.M.S., Brittan, P.,
Matching structural and implementational models in the specification of image classifiers,
PR(24), No. 6, 1991, pp. 555-566.
WWW Version. 0401
The parallel implementation of pattern recognition algorithms applied to image analysis tasks. BibRef

Wang, Y., Mangaser, A., Srinivasan, P., Jordan, S., Butner, S.,
The 3DP: A Processor Architecture for Three-Dimensional Applications,
Computer(25), No. 1, January 1992, pp. 25-36. BibRef 9201

Wallace, A.M., Michaelson, G.J., McAndrew, P., Waugh, K.G., Austin, W.J.,
Dynamic Control and Prototyping of Parallel Algorithms for Intermediate- and High-Level Vision,
Computer(25), No. 2, February 1992, pp. 43-53. BibRef 9202

Shieh, E., Current, K.W., Hurst, P.J., Agi, I.,
High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture,
CirSysVideo(2), No. 4, December 1992, pp. 347-360.
IEEE Top Reference. 0206
BibRef

Montani, C., Scopigno, R.,
Using Marching Cubes on Small Machines,
GMIP(56), No. 2, March 1994, pp. 182-183. BibRef 9403

Cantoni, V.,
New Architectural Solutions for Computer Vision Systems,
MVA(8), No. 2, 1995, pp. 77-78. BibRef 9500

Thirion, J.P., Gourdon, A.,
The 3D Marching Lines Algorithm,
GMIP(58), No. 6, November 1996, pp. 503-509. 9701
BibRef

Gehrke, W., Gaedke, K.,
Associative controlling of monolithic parallel processor architectures,
CirSysVideo(5), No. 5, October 1995, pp. 453-464.
IEEE Top Reference. 0206
BibRef

Dutta, S., Wolf, W.,
Asymptotic limits of video signal processing architectures,
CirSysVideo(5), No. 6, December 1995, pp. 545-561.
IEEE Top Reference. 0206
BibRef

Bader, D.A.[David A.], and JaJa, J.[Joseph],
Parallel Algorithms for Image Histogramming and Connected Components with an Experimental Study,
PDC(35), No. 2, 15 June 1996, pp. 173-190. BibRef 9606

Bader, D.A.[David A.], JaJa, J.[Joseph], Harwood, D.[David], and Davis, L.S.[Larry S.],
Parallel Algorithms for Image Enhancement and Segmentation by Region Growing with an Experimental Study,
UMIACS-TR-95-44. Institute for Advanced Computer Studies (UMIACS), University of Maryland, College Park, May 1995.
WWW Version. Uses Symmetric Neighborhood Filter. Implementation for a variety of multiple processors (CM-5, SP-2, etc.) and workstation clusters. BibRef 9505

Chakrabarti, C., JaJa, J.F.,
A parallel algorithm for template matching on an SIMD mesh connected computer,
ICPR90(II: 362-367).
IEEE DOI Link 9208
BibRef

Fountain, T.J.,
Array Architectures for Iconic and Symbolic Image Processing,
PRAI(2), 1988, pp. 407-424. BibRef 8800

Apffel, J.M., Current, K.W., Sanz, J.L.C., Jain, A.K.,
An Architecture for Region Boundary Extraction in Raster Scan Images Suitable for VLSI Implementation,
MVA(2), 1989, pp. 193-214. BibRef 8900

Yamashita, M.,
Parallel and Sequential Transformations on Digital Images,
PR(18), No. 1, 1985, pp. 31-41.
WWW Version. BibRef 8500
Earlier: PR(17), No. 6, 1984, pp. Page 677.
WWW Version. BibRef

Fischler, M.A., Firschein, O.,
Parallel Guessing: A Strategy for High-Speed Computation,
PR(20), No. 2, 1987, pp. 257-263.
WWW Version. BibRef 8700

Sleigh, A.C., Baily, P.K.,
DIPOD: An Image Understanding Development and Implementation System,
PRL(6), 1987, pp. 101-106. BibRef 8700

Amini, A.A., Weymouth, T.E., Anderson, D.J.,
A Parallel Algorithm for Determining Two-Dimensional Object Positions Using Incomplete Information About Their Boundaries,
PR(22), No. 1, 1989, pp. 21-28.
WWW Version. BibRef 8900

Kamada, M.[Masaru], Toraichi, K.[Kazuo], Mori, R.[Ryoichi], Yamamoto, K.[Kazuhiko], Yamada, H.[Hiromitsu],
A parallel architecture for relaxation operations,
PR(21), No. 2, 1988, pp. 175-181.
WWW Version. 0309
BibRef

Chen, Z., Lin, S.Y., Chen, Y.Y.,
A Parallel Architecture for Probabilistic Relaxation Operations on Images,
PR(23), No. 6, 1990, pp. 637-645.
WWW Version. Relaxation. BibRef 9000

Tanimoto, S.L., Kent, E.W.,
Architectures and Algorithms for Iconic-to-Symbolic Transformations,
PR(23), No. 12, 1990, pp. 1377-1388.
WWW Version. BibRef 9000

Tanimoto, S.L.,
An Iconic/Symbolic Data Structuring Scheme,
PRAI-76(452-471). BibRef 7600

Hwang, S.Y.[Shu-Yuen], Tanimoto, S.L.,
Parallel coordination of image operators based on shared-memory architecture,
ICPR90(II: 343-349).
IEEE DOI Link 9208
BibRef

Cheng, H.D., Tong, C., Lu, Y.J.,
VLSI Curve Detector,
PR(23), No. 1-2, 1990, pp. 35-50.
WWW Version. BibRef 9000

Lee, S.Y., Aggarwal, J.K.,
A System Design / Scheduling Strategy for Parallel Image Processing,
PAMI(12), No. 2, February 1990, pp. 194-204.
IEEE Abstract. IEEE Top Reference.
WWW Version. BibRef 9002

Inoue, K., Nakamura, A., Nivat, M., Saoudi, A., Wang, P.S.P., (Eds.)
Special Issue on Parallel Image Analysis and Processing,
PRAI(8), No. 2, April 1994, pp. 415-639. Papers from a workshop. BibRef 9404

Seetharaman, G.[Guna],
A Simplified Design Strategy for Mapping Image Processing Algorithms on a SIMD Torus,
TCS(140), No. 2, April 1995, pp. 319-331. BibRef 9504

Morita, K., Nakamura, A., Nivat, M., Wang, P.S.P.,
Special Issue: Parallel Image Analysis,
PRAI(13), No. 4, June 1999, pp. 429. 0005
BibRef

Brown, J., Crookes, D.,
A High Level Language for Parallel Image Processing,
IVC(12), No. 2, March 1994, pp. 67-79.
WWW Version. BibRef 9403

Crookes, D., Benkrid, K., Bouridane, A., Alotaibi, K., Benkrid, A.,
Design and implementation of a high level programming environment for FPGA-based image processing,
VISP(147), No. 4, 2000, pp. 377. 0010
BibRef

Crookes, D., Alotaibi, K., Bouridane, A., Donachy, P., Benkrid, A.,
An environment for generating FPGA architectures for image algebra-based algorithms,
ICIP98(III: 990-994).
IEEE DOI Link 9810
BibRef

Regli, W.C., Gupta, S.K., Nau, D.S.,
Towards Multiprocessor Feature Recognition,
CAD(29), No. 1, January 1997, pp. 37-51. 9702
BibRef

McCall, J.T., Tront, J.G., Gray, F.G., Haralick, R.M., McCormack, W.M.,
Parallel Computer Architectures and Problem Solving Strategies for the Consistent Labeling Problem,
TC(34), 1985, pp. 937-980. BibRef 8500

Wang, C.L., Bhat, P.B., Prasanna, V.K.,
High-Performance Computing for Vision,
PIEEE(84), No. 7, July 1996, pp. 931-946. 9607
BibRef

Cucchiara, R., di Stefano, L., Piccardi, M., Cinotti, T.S.,
The Giotto System: a Parallel Computer for Image Processing,
RealTimeImg(3), No. 5, October 1997, pp. 343-353. 9712
BibRef

Brown, C.R., Harrison, S., Furness, P.,
Exploiting IEEE-1355 Routable Serial Links in a Real Time Vision Architecture,
RealTimeImg(3), No. 5, October 1997, pp. 355-361. 9712
BibRef

Armstrong, J.B., Maheswaran, M., Theys, M.D., Siegel, H.J., Nichols, M.A., Casey, K.H.,
Parallel Image Correlation: Case-Study to Examine Trade-Offs in Algorithm-to-Machine Mappings,
Super(12), No. 1-2, 1998, pp. 7-35. 9805
BibRef

Mabin, F.H., Mongenet, C.,
A Parallel Algorithm to Reconstruct Bounding Surfaces in 3D Images,
Super(12), No. 1-2, 1998, pp. 137-155. 9805
BibRef

Juhasz, Z.,
An Analytical Method for Predicting the Performance of Parallel Image-Processing Operations,
Super(12), No. 1-2, 1998, pp. 157-174. 9805
BibRef

Fleury, M., Clark, A.F.,
Parallelizing a Set of 2-D Frequency Transforms in a Flexible Manner,
VISP(145), No. 1, February 1998, pp. 65-72. 9804
BibRef
Earlier:
Performance prediction for parallel reconfigurable low-level image processing,
ICPR94(C:349-351).
IEEE DOI Link 9410
BibRef

Landraudlamole, A.M.,
Principle of a Parallel Vision System Adapted to Textures: A Theoretical Solution for Selecting Visual Filters,
PRAI(12), No. 3, May 1998, pp. 355-378. 9807
BibRef

Portnoff, M.R.,
An efficient method for transposing large matrices and its application to separable processing of two-dimensional signals,
IP(2), No. 1, January 1993, pp. 122-124.
IEEE DOI Link 0402
BibRef

Portnoff, M.R.,
An Efficient Parallel-Processing Method for Transposing Large Matrices in Place,
IP(8), No. 9, September 1999, pp. 1265-1275.
IEEE DOI Link BibRef 9909

Vorontsov, M.A.[Mikhail A.],
Parallel image processing based on an evolution equation with anisotropic gain: integrated optoelectronic architectures,
JOSA-A(16), No. 7, July 1999, pp. 1623-1637. BibRef 9907

Mattson, P.[Peter], Basoglu, C.[Chris], Kim, Y.M.[Yong-Min],
Interactive Image Morphing on a Single-Chip Multiprocessor using a Multilayered Parallel Image Computing Library,
RealTimeImg(6), No. 3, June 2000, pp. 175-183. 0008
BibRef

Bharadwaj, V., Li, X.L.[Xiao-Lin], Ko, C.C.[Chi Chung],
Efficient partitioning and scheduling of computer vision and image processing data on bus networks using divisible load analysis,
IVC(18), No. 11, August 2000, pp. 919-938.
WWW Version. 0006
BibRef

Torres, F., Candelas, F.A., Puente, S.T., Ortiz, F.G.,
Graph models applied to specification, simulation, allocation, and scheduling of real-time computer vision applications,
IJIST(11), No. 5, 2000, pp. 287-291.
WWW Version. 0110
BibRef

Torres, F., Candelas, F.A., Puente, S.T., Jiménez, L.M., Fernández, C., Agulló, R.J.,
Simulation and Scheduling of Real-Time Computer Vision Algorithms,
CVS99(98 ff.).
HTML Version. 0209
BibRef

Kyrki, V.[Ville], Peusaari, J.[Jani], Kälviäinen, H.[Heikki],
Intermediate-level feature extraction in novel parallel environments,
MVA(13), No. 5-6, 2003, pp. 363-371.
HTML Version. 0304
BibRef

Lee, S.W.[Shin-Wen], Hsu, W.H.[Wen-Hsing],
Parallel algorithms for hidden markov models on the orthogonal multiprocessor,
PR(25), No. 2, February 1992, pp. 219-232.
WWW Version. 0401
See also Parallel implementation of prime-factor discrete cosine transform on the orthogonal multiprocessor. BibRef

Coudarcher, R.[Rémi], Duculty, F.[Florent], Serot, J.[Jocelyn], Jurie, F.[Frédéric], Derutin, J.P.[Jean-Pierre], Dhome, M.[Michel],
Managing Algorithmic Skeleton Nesting Requirements in Realistic Image Processing Applications: The Case of the SKiPPER-II Parallel Programming Environment's Operating Model,
JASP(2005), No. 7, 2005, pp. 1005-1023.
WWW Version. 0603
BibRef

Macpherson, K.N., Stewart, R.W.,
Area efficient FIR filters for high speed FPGA implementation,
VISP(153), No. 6, December 2006, pp. 711-720.
WWW Version. 0702
BibRef

Mckeown, M.A., Lindsay, I.A.B., Cruickshank, D.G.M., Thompson, J.S., Farson, S.A., Hu, Y.,
Re-scalable V-BLAST MIMO system for FPGA,
VISP(153), No. 6, December 2006, pp. 747-753.
WWW Version. 0702
BibRef

Davis, L.S.,
Parallel Image analysis: Theory and Applications,
World Scientific1995, ISBN: 981-02-2476-1
WWW Version. BibRef 9500

Ghazal, M., Amer, A.[Aishy], Ghrayeb, A.,
A Real-Time Technique for Spatio-Temporal Video Noise Estimation,
CirSysVideo(17), No. 12, December 2007, pp. 1690-1699.
IEEE DOI Link 0712
BibRef

Lapalme, F.X., Amer, A., Wang, C.Y.[Chun-Yan],
FPGA Architecture for Real-Time Video Noise Estimation,
ICIP06(3257-3260). 0610

IEEE DOI Link BibRef

Ratnayake, K.[Kumara], Amer, A.[Aishy],
Sequential, Irregular and Complex Object Contour Tracing on FPGA,
ICIP07(V: 165-168).
IEEE DOI Link 0709
BibRef
Earlier:
An FPGA-Based Implementation of Spatio-Temporal Object Segmentation,
ICIP06(3265-3268). 0610

IEEE DOI Link BibRef

Quinn, H.[Heather], Leeser, M.[Miriam], King, L.S.[Laurie Smith],
Dynamo: a runtime partitioning system for FPGA-based HW/SW image processing systems,
RealTimeIP(2), No. 4, December 2007, pp. 179-190.
Springer DOI Link 0712
BibRef

Lindoso, A.[Almudena], Entrena, L.[Luis],
High performance FPGA-based image correlation,
RealTimeIP(2), No. 4, December 2007, pp. 223-233.
Springer DOI Link 0712
BibRef

Smach, F.[Fethi], Miteran, J.[Johel], Atri, M.[Mohamed], Dubois, J.[Julien], Abid, M.[Mohamed], Gauthier, J.P.[Jean-Paul],
An FPGA-based accelerator for Fourier Descriptors computing for color object recognition using SVM,
RealTimeIP(2), No. 4, December 2007, pp. 249-258.
Springer DOI Link 0712
BibRef

Mitéran, J.[Johel], Zimmer, J.P.[Jean-Philippe], Paindavoine, M.[Michel], Dubois, J.[Julien],
Real-Time 3D Face Acquisition Using Reconfigurable Hybrid Architecture,
JIVP(2007), 2007, pp. xx-yy.
WWW Version. 0804
BibRef

Smach, F.[Fethi], Lemaître, C.[Cedric], Gauthier, J.P.[Jean-Paul], Miteran, J.[Johel], Atri, M.[Mohamed],
Generalized Fourier Descriptors with Applications to Objects Recognition in SVM Context,
JMIV(30), No. 1, January 2008, pp. 43-71.
Springer DOI Link 0801
BibRef

Caarls, W.[Wouter], Jonker, P.[Pieter], Corporaal, H.[Henk],
Skeletons and Asynchronous RPC for Embedded Data and Task Parallel Image Processing,
IEICE(E89-D), No. 7, July 2006, pp. 2036-2043.
WWW Version. 0607
BibRef

Siozios, K.[Kostas], Soudris, D.[Dimitrios],
Designing a novel high-performance FPGA architecture for data intensive applications,
RealTimeIP(4), No. 2, June 2009, pp. xx-yy.
Springer DOI Link 0905
BibRef

Zhou, H.P.[Hong-Ping], Guo, L.[Li],
Self-adaptive frequency agility realized with FPGA,
IASP09(419-422).
IEEE DOI Link 0904
BibRef

Jaime, F.J.[Francisco J.], Hormigo, J.[Javier], Villalba, J.[Julio], Zapata, E.L.[Emilio L.],
New SIMD instructions set for image processing applications enhancement,
ICIP08(1396-1399).
IEEE DOI Link 0810
BibRef

Afrah, A.[Amir], Miller, G.[Gregor], Parks, D.[Donovan], Finke, M.[Matthias], Fels, S.[Sidney],
Hive: A distributed system for vision processing,
ICDSC08(1-9).
IEEE DOI Link 0809
BibRef

Salem, M.A.M.[Mohammed A-Megeed], Appel, M.[Markus], Winkler, F.[Frank], Meffert, B.[Beate],
FPGA-based Smart Camera for 3D wavelet-based image segmentation,
ICDSC08(1-8).
IEEE DOI Link 0809
BibRef

Dias, F., Berry, F., Serot, J., Marmoiton, F.,
Hardware, Design and Implementation Issues on a FPGA-Based Smart Camera,
ICDSC07(20-26).
IEEE DOI Link 0709
BibRef

van der Wal, G.S.[Gooitzen S.], Brehm, F.[Frederic], Piacentino, M.[Michael], Marakowitz, J.[James], Gudis, E.[Eduardo], Sufi, A.[Azhar], Montante, J.[James],
An FPGA-Based Verification Framework for Real-Time Vision Systems,
EmbedCV06(124).
IEEE DOI Link 0609
BibRef

Abel, N., Kessal, L., Demigny, D.,
Design flexibility using FPGA dynamical reconfiguration,
ICIP04(IV: 2821-2824).
IEEE DOI Link 0505
BibRef

Johnston, D.J., Fleury, M., Downton, A.C.,
An event-based execution model for efficient image processing on workstation clusters and the grid,
ICPR04(I: 732-735).
IEEE DOI Link 0409
BibRef

Martina, M., Molino, A., Terreno, A., Pacca, F.,
Implementation of a SPIHT coprocessor memory issues and hardware implications,
ICIP03(II: 587-590).
IEEE Abstract. IEEE Top Reference. 0312
BibRef

Gentile, A., Wills, D.S.,
Impact of pixel per processor ratio on embedded SIMD architectures,
CIAP01(204-208).
IEEE Top Reference. 0210
BibRef

Leo, C.S., Schroder, H.,
Fast processing of medical images using a new parallel architecture, the hybrid system,
Southwest02(148-152).
IEEE Top Reference. 0208
BibRef

López-de-Teruel, P.E., Ruiz, A., García, J.M.,
A Parallel Algorithm for Tracking of Segments in Noisy Edge Images,
ICPR00(Vol IV: 807-811).
IEEE DOI Link
HTML Version. 0009
BibRef

Seinstra, F.J., Koelma, D.C.,
Transparent Parallel Image Processing by Way of a Familiar Sequential API,
ICPR00(Vol IV: 824-827).
IEEE DOI Link
HTML Version. 0009
BibRef

Mengko, T.L., Adiono, T., Setyawan, H., Setiadarma, R., Hudiansyah, D.A.,
Design and Implementation of Real Time System for Object Detection and Classification on Parallel Virtual Machine,
MVA98(xx-yy). BibRef 9800

You, J., Sattar, A., Vlavic, L.,
Parallel Vision Computing on a Network of Workstation Clusters,
MVA98(xx-yy). BibRef 9800

Wiatr, K.[Kazimierz],
Dedicated hardware processors for a real-time image data pre-processing implemented in FPGA structure,
CIAP97(II: 69-76).
WWW Version. 9709
BibRef

Jonker, P.P.[Peter P.],
An SIMD-MIMD Architecture for Image Processing and Pattern Recognition,
CAMP93(222-230). BibRef 9300

Gerogiannus, D.C., Orphanoudakis, S.C.,
Load Balancing Requirement In Parallel Implementations Of Image Feature Extraction Tasks,
PDS(4), 1993, pp. 994-1013. BibRef 9300
Earlier:
Efficient use of parallelism in intermediate level vision tasks,
ICPR92(IV:160-164).
IEEE DOI Link 9208
BibRef
Earlier:
Efficient embedding of interprocessor communications in parallel implementations of intermediate level vision tasks,
ICPR90(II: 368-372).
IEEE DOI Link 9208
BibRef

Brunzema, M., Burmeister, H., Gerogiannis, D.C.,
Parallelization of an image analysis application: Problems, results and a solution framework,
ICPR94(C:406-411).
IEEE DOI Link 9410
BibRef

Gerogiannis, D.C.,
Programming intermediate level vision tasks on parallel machines,
ICPR92(IV:119-123).
IEEE DOI Link 9208
BibRef

Willis, J.C.[John C.], and Sanderson, A.C.[Arthur C.],
RAPIDbus, Architecture and Realization,
CMU-RI-TR-82-13, CMU Robotics Institute. 1982. Implementation of a cross bar switch using a multiplexed very high bandwidth bus. BibRef 8200

Yoshii, H.,
Binary Pact,
ICPR96(IV: 606-610).
IEEE DOI Link 9608
(Canon Inc., J) BibRef

Spieth, M.R., Hulskamp, J.P.,
Parallel image processing on single processor systems,
ICIP96(II: 133-136).
IEEE DOI Link 9610
BibRef

Wu, A.Y.[An-Yeu], Liu, K.J.R., Raghupathy, A., Liu, S.C.[Shang-Chieh],
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Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
GPU Implementations and Algorithms for Image Processing and Computer Vision .