19.2.6.1 Reconfigurable Mesh Architectures and Algorithms

Miller, R., and Stout, Q.F.[Quentin F.],
Geometric Algorithms for Digitized Pictures on a Mesh-Connected Computer,
PAMI(7), No. 2, March 1985, pp. 216-228. See also Convexity Algorithms for Parallel Machines. BibRef 8503

Miller, R., Prasanna-Kumar, V.K., Reisis, D.I., Stout, Q.F.,
Image Computations on Reconfigurable VLSI Arrays,
CVPR88(925-930).
IEEE Abstract. IEEE Top Reference. BibRef 8800

Bondalapati, K., Prasanna, V.K.,
Reconfigurable computing systems,
PIEEE(90), No. 7, July 2002, pp. 1201-1217.
IEEE DOI Link 0207
BibRef

Kasabov, N.K.,
Functionally Reconfigurable General Purpose Parallel Machines and Some Image Processing and Pattern Recognition Applications,
PRL(3), 1985, pp. 215-223. BibRef 8500

Shapiro, L.G.[Linda G.], Haralick, R.M.[Robert M.], and Goulish, M.J.[Micheal J.],
Insight: A Data Flow Language for Programming Vision Algorithms in a Reconfigurable Computational Network,
PRAI(1), No. 3, 1987, pp. 335-350. BibRef 8700

Siegel, H.J., Armstrong, J.B., Watson, D.W.,
Mapping Computer-Vision-Related Tasks onto Reconfigurable Parallel-Processing Systems,
Computer(25), No. 2, February 1992, pp. 54-62. BibRef 9202

Olariu, S., Schwing, J.L., Zhang, J.,
Fast Computer Vision Algorithms for Reconfigurable Meshes,
IVC(10), No. 9, November 1992, pp. 610-616.
WWW Version. BibRef 9211

Olariu, S., Schwing, J.L., Zhang, J.,
Computing the Hough Transform on Reconfigurable Meshes,
IVC(11), No. 10, December 1993, pp. 623-628.
WWW Version. BibRef 9312

Jang, J.W., Park, H., Prasanna, V.K.,
A Fast Algorithm for Computing a Histogram on Reconfigurable Mesh,
PAMI(17), No. 2, February 1995, pp. 97-106.
IEEE Abstract. IEEE Top Reference.
WWW Version. BibRef 9502

Haralick, R.M., Somani, A.K., Wittenbrink, C.M., Johnson, R., Cooper, K., Shapiro, L.G., Phillips, I.T., Hwang, J.N., Cheung, W., Yao, Y.H., Chen, C.H., Yang, L., Daughterty, B., Lorbeski, B., Loving, K., Miller, T., Parkins, L., Soos, S.,
Proteus: A Reconfigurable Computational Network for Computer Vision,
MVA(8), No. 2, 1995, pp. 85-100. BibRef 9500
Earlier: ICPR92(IV:43-54).
IEEE DOI Link BibRef

Kanungo, T., Chiou, G.I., Somani, A.K., Haralick, R.M.,
Morphological image processing on a token passing pyramid computer,
ICPR92(IV:83-86).
IEEE DOI Link 9208
BibRef

Anguita, D.[Davide], di Gesù, V.[Vito], Gerardi, G.[Gaetano], Lenzitti, B.[Biagio], Tegolo, D.[Domenico],
A Heterogeneous and Reconfigurable Machine-Vision System,
MVA(8), No. 5, 1995, pp. 343-350.
HTML Version. BibRef 9500

Tegolo, D.[Domenico], Lenzitti, B.[Biagio], Isgro, F., di Gesù, V.[Vito],
Dynamic interface for machine vision systems,
ICPR94(C:323-326).
IEEE DOI Link 9410
BibRef

Tsai, H.R., Horng, S.J., Lee, S.S., Tsai, S.S., Kao, T.W.,
Parallel Hierarchical-Clustering Algorithms on Processor Arrays with a Reconfigurable Bus System,
PR(30), No. 5, May 1997, pp. 801-815.
WWW Version. 9705
See also Image-Processing on a Reconfigurable Array of Processors with Wider Bus Networks. Clustering. BibRef

Tsai, H.R., Horng, S.J.,
Optimal parallel clustering algorithms on a reconfigurable array of processors with wider bus networks,
IVC(17), No. 13, 1 November 1999, pp. 925-936.
WWW Version. 9911
BibRef

Tsai, H.R.[Horng-Ren], Horng, S.J.[Shi-Jinn], Tsai, S.S.[Shun-Shan], Lee, S.S.[Shung-Shing], Kao, T.W.[Tzong-Wann], Chen, C.H.[Chia-Ho],
Optimal Speed-Up Parallel Image Template Matching Algorithms on Processor Arrays with a Reconfigurable Bus System,
CVIU(71), No. 3, September 1998, pp. 393-412.
WWW Version. BibRef 9809

Lee, S.S., Horng, S.J., Tsai, H.R., Lee, Y.H.,
Image-Processing on a Reconfigurable Array of Processors with Wider Bus Networks,
PR(30), No. 9, September 1997, pp. 1521-1532.
WWW Version. 9708
See also Optimal Computing Hough Transform on a Reconfigurable Array of Processors with Wider Bus Networks. and See also Parallel Hierarchical-Clustering Algorithms on Processor Arrays with a Reconfigurable Bus System. BibRef

Lee, S.S., Horng, S.J., Tsai, H.R.,
Entropy Thresholding and Its Parallel Algorithm on the Reconfigurable Array of Processors with Wider Bus Networks,
IP(8), No. 9, September 1999, pp. 1229-1242.
IEEE DOI Link See also Optimal Computing Hough Transform on a Reconfigurable Array of Processors with Wider Bus Networks. BibRef 9909

Wu, C.H.[Chin-Hsiung], Horng, S.J.[Shi-Jinn], Chen, Y.W.[Yi-Wen], Lee, W.Y.[Wei-Yi],
Designing scalable and efficient parallel clustering algorithms on arrays with reconfigurable optical buses,
IVC(18), No. 13, October 2000, pp. 1033-1043.
WWW Version. 0008
BibRef

Chung, K.L.[Kuo-Liang],
Constant-Time Thresholding on Reconfigurable Mesh,
RealTimeImg(5), No. 2, April 1999, pp. 77-81. BibRef 9904

Loui, A.C.P., Venetsanopoulos, A.N., Smith, K.C.,
Flexible architectures for morphological image processing and analysis,
CirSysVideo(2), No. 1, March 1992, pp. 72-83.
IEEE Top Reference. 0206
BibRef

Bove, Jr., V.M., Watlington, J.A.,
Cheops: a reconfigurable data-flow system for video processing,
CirSysVideo(5), No. 2, April 1995, pp. 140-149.
IEEE Top Reference. 0206
BibRef

Boluda, J.A.[Jose Antonio], Pardo, F.[Fernando],
A reconfigurable architecture for autonomous visual-navigation,
MVA(13), No. 5-6, 2003, pp. 322-331.
HTML Version. 0304
BibRef

Dias, T.[Tiago], Roma, N.[Nuno], Sousa, L.[Leonel], Ribeiro, M.[Miguel],
Reconfigurable architectures and processors for real-time video motion estimation,
RealTimeIP(2), No. 4, December 2007, pp. 191-205.
Springer DOI Link 0712
BibRef

Denoulet, J.[Julien], Mérigot, A.[Alain],
An architecture based on reconfigurability and asynchronism for real-time image processing,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI Link 0804
BibRef

Kessal, L.[Lounis], Abel, N.[Nicolas], Karabernou, S.M.[Si Mahmoud], Demigny, D.[Didier],
Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI Link 0804
BibRef

Chai, S.M.[Sek M.], Bellas, N.[Nikolaos], Kujawa, G.[Greg], Ziomek, T.[Tom], Dawson, L.[Linda], Scaminaci, T.[Tony], Dwyer, M.[Malcolm], Linzmeier, D.[Dan],
Reconfigurable Streaming Architectures for Embedded Smart Cameras,
EmbedCV06(122).
IEEE DOI Link 0609
BibRef

Arnabat, J., Cardells, F.,
Flexible Hardware Architecture for 2D Seprable Scaling Using Convolution Interpolation,
SIPS05(688-692).
HTML Version. BibRef 0500

Ahmedsaid, A., Amira, A.,
Accelerating svd on reconfigurable hardware for image denoising,
ICIP04(I: 259-262).
IEEE DOI Link 0505
BibRef

Khan, A.I., Mihailescu, P.,
Parallel pattern recognition computations within a wireless sensor network,
ICPR04(I: 777-780).
IEEE DOI Link 0409
BibRef

Benitez, D.[Domingo], Cabrera, J.[Jorge],
Reactive Computer Vision System with Reconfigurable Architecture,
CVS99(348 ff.).
HTML Version. 0209
BibRef

Bugeja, A.[Alexander], Yang, W.[Woodward],
A Coarse-Grained, Reconfigurable Image Coprocessor,
DARPA97(1389-1392). BibRef 9700

Serra, J.R., Subirana, J.B.[J. Brian],
Adaptive non-cartesian networks for vision,
CIAP97(II: 324-331).
WWW Version. 9709
BibRef

Bhandarkar, S.M., Arabnia, H.R.,
Parallelization of Computer Vision Algorithms on a Reconfigurable Multiprocessor,
ICPR94(C:240-244).
IEEE DOI Link BibRef 9400

Praud, S.[Stéphane], Germain, P.[Pierre], Plantier, J.[Justin],
Prototyping of interactive satellite image analysis tools using a real-time data-flow computer,
CIAP95(683-688).
Springer DOI Link 9509
BibRef

Lee, C.W.[Cheol-Whan], Wang, Y.F.[Yuan-Fang], Yang, T.[Tao],
Static global scheduling for optimal computer vision and image processing operations on distributed-memory multiprocessors,
CAIP95(920-925).
Springer DOI Link 9509
BibRef

Goodenough, J., Shelley, A.J., Seed, N.L.,
HART, a heterogeneous architecture for real-time prototyping, development and implementation of machine vision applications,
ICIP94(III: 678-680).
IEEE DOI Link 9411
BibRef

Leite, N.J., de Barros, M.A.,
A highly reconfigurable neighborhood image processor based on functional programming,
ICIP94(III: 659-663).
IEEE DOI Link 9411
BibRef

Weil, F.J., Jamieson, L.H., Delp, E.J.,
Dynamic intelligent scheduling and control of reconfigurable parallel architectures for computer vision/image processing,
ICPR90(II: 318-323).
IEEE DOI Link 9208
BibRef

Samal, A.,
Design of a dynamically reconfigurable, integrated, parallel vision system,
ICPR90(II: 521-523).
IEEE DOI Link 9208
BibRef

Chianese, A., Cordella, L.P., de Santo, M., Marcelli, A., Vento, M.,
A preliminary approach to the design and evaluation of a reconfigurable architecture for computer vision,
ICPR88(II: 724-726).
IEEE DOI Link 8811
BibRef

Garda, P., Reichart, A., Rodriguez, H., Devos, F., Zavidovique, B.,
Yet another mesh array smart sensor?,
ICPR88(II: 863-865).
IEEE DOI Link 8811
BibRef

Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
Multi-Processor Algorithms, Pyramid Machines .