Keith Price Bibliography Hardware, VLSI Implementations, Embedded Processors, Sensor Processing

Moini, A.[Alireza],
Vision Chips,
KluwerOctober 1999. ISBN 0-7923-8664-7
WWW Version. smart visual sensors, are those sensors that have integrated image acquisition and parallel processing, often at the pixel level, using dedicated analog and digital circuits. BibRef 9910

Roska, T.[Tamás], Rodriguez-Vazquez, A.,
Toward visual microprocessors,
PIEEE(90), No. 7, July 2002, pp. 1244-1257.
IEEE DOI Link 0207
BibRef

Roska, T.[Tamás],
The analogic single-chip CNN visual supercomputer: A review,
CAIP93(813-821).
Springer DOI Link 9309
BibRef

Wu, B.F.[Bing-Fei], Hu, Y.Q.A.[Yi-Qi-Ang],
An efficient VLSI implementation of the discrete wavelet transform using embedded instruction codes for symmetric filters,
CirSysVideo(13), No. 9, September 2003, pp. 936-943.
IEEE Abstract. IEEE Top Reference. 0310
BibRef

Kessal, L., Abel, N., Demigny, D.,
Real-time image processing with dynamically reconfigurable architecture,
RealTimeImg(9), No. 5, October 2003, pp. 297-313.
WWW Version. 0311
BibRef

Kessal, L., Demigny, D., Boudouani, N., Bourgiba, R.,
Reconfigurable Hardware for Real Time Image Processing,
ICIP00(Vol III: 110-113).
IEEE Abstract. IEEE Top Reference. 0008
BibRef

Fürtler, J.[Johannes], Mayer, K.J.[Konrad J.], Krattenthaler, W.[Werner], Bajla, I.[Ivan],
SPOT: Development tool for software pipeline optimization for VLIW-DSPs used in real-time image processing,
RealTimeImg(9), No. 6, December 2003, pp. 387-399.
WWW Version. 0401
BibRef

Draper, B.A., Beveridge, J.R., Bohm, A.P.W., Ross, C., Chawathe, M.,
Accelerated image processing on FPGAs,
IP(12), No. 12, December 2003, pp. 1543-1551.
IEEE DOI Link 0402
BibRef
Earlier:
Implementing image applications on FPGAs,
ICPR02(III: 265-268).
IEEE DOI Link 0211
BibRef

Lu, C.K., Summerfield, S.,
Design and VLSI implementation of QMF banks,
VISP(151), No. 5, October 2004, pp. 421-427.
IEEE Abstract. IEEE Top Reference. 0501
BibRef

Huang, C.T., Tseng, P.C., Chen, L.G.,
Generic RAM-Based Architectures for Two-Dimensional Discrete Wavelet Transform With Line-Based Method,
CirSysVideo(15), No. 7, July 2005, pp. 910-920.
IEEE DOI Link 0508
BibRef

Artyomov, E., Rivenson, Y., Levi, G., Yadid-Pecht, O.,
Morton (Z) Scan Based Real-Time Variable Resolution CMOS Image Sensor,
CirSysVideo(15), No. 7, July 2005, pp. 947-952.
IEEE DOI Link 0508
BibRef

Bishnu, A., Bhattacharya, B.B., Kundu, M.K., Murthy, C.A., Acharya, T.,
Euler vector for search and retrieval of gray-tone images,
SMC-B(35), No. 4, August 2005, pp. 801-812.
IEEE DOI Link 0508
BibRef
Earlier:
On-chip Computation of Euler Number of a Binary Image for Efficient Database Search,
ICIP01(III: 310-313).
IEEE Abstract. IEEE Top Reference. 0108
BibRef

Bishnu, A., Bhunre, P.K., Bhattacharya, B.B., Kundu, M.K., Murthy, C.A.,
Content Based Image Retrieval: Related Issues Using Euler Vector,
ICIP02(II: 585-588).
IEEE Abstract. IEEE Top Reference. 0210
BibRef

Bolcioni, L., Campi, F., Canegallo, R., Guerrieri, R.,
A low-power system-on-chip for the documentation of road accidents,
CirSysVideo(15), No. 11, November 2005, pp. 1493-1501.
IEEE DOI Link 0512
BibRef

Martina, M.[Maurizio], Masera, G.[Guido],
Mumford and Shah Functional: VLSI Analysis and Implementation,
PAMI(28), No. 3, March 2006, pp. 487-494.
IEEE DOI Link 0602
See also Optimal Approximations by Piecewise Smooth Functions and Variational Problems. BibRef

Reyna-Rojas, R.[Roberto], Houzet, D.[Dominique], Dragomirescu, D.[Daniela], Carlier, F.[Florent], Ouadjaout, S.[Salim],
Object Recognition System-on-Chip Using the Support Vector Machines,
JASP(2005), No. 7, 2005, pp. 993-1004.
WWW Version. 0603
BibRef

Barbaro, M.[Massimo], Raffo, L.[Luigi],
A Low-Power Integrated Smart Sensor with on-Chip Real-Time Image Processing Capabilities,
JASP(2005), No. 7, 2005, pp. 1062-1070.
WWW Version. 0603
BibRef

Kleihorst, R.P.[Richard P.], Abbo, A.A.[Anteneh A.], Choudhary, V.[Vishal], Broers, H.[Harry],
Scalable IC Platform for Smart Cameras,
JASP(2005), No. 13, 2005, pp. 2018-2025.
WWW Version. 0603
BibRef

Kleihorst, R.P.[Richard P.], Abbo, A.A.[Anteneh A.], Schueler, B.[Ben], Danilin, A.[Alexander],
Camera Mote with a High-Performance Parallel Processor for Real-Time Frame-Based Video Processing,
AVSBS07(69-74).
IEEE DOI Link 0709
BibRef
And: ICDSC07(109-116).
IEEE DOI Link 0709
BibRef

Fischer, V.[Viktor], Lukac, R.[Rastislav], Martin, K.[Karl],
Cost-Effective Video Filtering Solution for Real-Time Vision Systems,
JASP(2005), No. 13, 2005, pp. 2026-2042.
WWW Version. 0603
BibRef

Wang, D., Yu, N., Gao, Y., Zhang, R.,
Effective correlation vector quantisation algorithm and its VLSI architecture,
VISP(153), No. 6, December 2006, pp. 735-738.
WWW Version. 0702
BibRef

Bensaali, F., Amira, A.,
Field programmable gate array based parallel matrix multiplier for 3D affine transformations,
VISP(153), No. 6, December 2006, pp. 739-746.
WWW Version. 0702
BibRef

Dang, P.[Philip],
VLSI architecture for real-time image and video processing systems,
RealTimeIP(1), No. 1, October 2006, pp. 57-62.
Springer DOI Link 0001
BibRef

Dandekar, O.[Omkar], Castro-Pareja, C.[Carlos], Shekhar, R.[Raj],
FPGA-based real-time 3D image preprocessing for image-guided medical interventions,
RealTimeIP(1), No. 4, July 2007, pp. 285-301.
Springer DOI Link 0707
BibRef

Saponara, S.[Sergio], Fanucci, L.[Luca], Marsi, S.[Stefano], Ramponi, G.[Giovanni],
Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing,
RealTimeIP(1), No. 4, July 2007, pp. 267-283.
Springer DOI Link 0707
BibRef

Saponara, S.[Sergio], Casula, M.[Michele], Fanucci, L.[Luca],
ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI Link 0804
BibRef

Banerjee, S., Evans, B.L.,
In-Camera Automation of Photographic Composition Rules,
IP(16), No. 7, July 2007, pp. 1807-1820.
IEEE DOI Link 0707
BibRef

Cheng, C.C., Huang, C.T., Chen, C.Y., Lian, C.J., Chen, L.G.,
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform,
CirSysVideo(17), No. 7, July 2007, pp. 814-822.
IEEE DOI Link 0707
BibRef

Kumaki, T.[Takeshi], Kono, Y.[Yutaka], Ishizaki, M.[Masakatsu], Koide, T.[Tetsushi], Mattausch, H.J.[Hans Jürgen],
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory,
IEICE(E90-D), No. 1, January 2007, pp. 346-354.
WWW Version. 0701
BibRef

Chandrasekaran, S.[Shrutisagar], Amira, A.[Abbes], Minghua, S.[Shi], Bermak, A.[Amine],
An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI Link 0804
BibRef

Sriram, V.[Vinay], Kearney, D.[David],
Multiple parallel FPGA implementations of a Kolmogorov phase screen generator,
RealTimeIP(3), No. 3, September 2008, pp. xx-yy.
Springer DOI Link 0804
BibRef

Chen, J.C., Chien, S.Y.,
CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders,
CirSysVideo(18), No. 9, September 2008, pp. 1223-1236.
IEEE DOI Link 0810
BibRef

Hiromoto, M., Sugano, H., Miyamoto, R.,
Partially Parallel Architecture for AdaBoost-Based Detection With Haar-Like Features,
CirSysVideo(19), No. 1, January 2009, pp. 41-52.
IEEE DOI Link 0902
BibRef

Hiromoto, M.[Masayuki], Nakahara, K.[Kentaro], Sugano, H.[Hiroki], Nakamura, Y.[Yukihiro], Miyamoto, R.[Ryusuke],
A Specialized Processor Suitable for AdaBoost-Based Detection with Haar-like Features,
EmbedCV07(1-8).
IEEE DOI Link 0706
BibRef

Razeghi, M., Hoffman, D., Nguyen, B.M., Delaunay, P.Y., Huang, E.K., Tidrow, M.Z., Nathan, V.,
Recent Advances in LWIR Type-II InAs/GaSb Superlattice Photodetectors and Focal Plane Arrays at the Center for Quantum Devices,
PIEEE(97), No. 6, June 2009, pp. 1056-1066.
IEEE DOI Link 0905
BibRef

Caulfield, J.T., McCarley, P.L., Elliott, J., Massie, M.A.,
Bandwidth efficient sensor architectures with feature extraction,
AIPR08(1-5).
IEEE DOI Link 0810
Focal Plane Array processors. BibRef

Cook, S., Harsanyi, J.,
Onboard processor for compressing HSI data,
AIPR02(200-204).
IEEE DOI Link 0210
BibRef

Wall, G., Iqbal, F., Isaacs, J., Liu, X.W.[Xiu-Wen], Foo, S.,
Real time texture classification using field programmable gate arrays,
AIPR04(130-135).
IEEE DOI Link 0410
BibRef

Li, H.Y.[Hui-Ya], Hwang, W.J.[Wen-Jyi], Hsu, C.C.[Chih-Chieh], Hung, C.L.[Chia-Lung],
Efficient K-Means VLSI Architecture for Vector Quantization,
SCIA09(440-449).
Springer DOI Link 0906
BibRef

Boudabous, A., Atitallah, A.B.[A. Ben], Kadionik, P., Khriji, L., Masmoudi, N.,
FPGA Codesign Implementation of Vector Directional Filter,
IPTA08(1-5).
IEEE DOI Link 0811
BibRef

Tan, J.Y.[Jun-Yan], Zhang, L.L.[Lin-Lin], Fresse, V.[Virginie], Legrand, A.C.[Anne Claire], Houzet, D.[Dominique],
A predictive and parametrized architecture for image analysis algorithm implementations on FPGA adapted to multispectral imaging,
IPTA08(1-8).
IEEE DOI Link 0811
BibRef

Atani, R.E.[R. Ebrahimi], Mirzakuchaki, S., Atani, S.E.[S. Ebrahimi],
Design and Implementation of an Image CoProcessor,
ICISP08(498-507).
Springer DOI Link 0807
BibRef

Diaz, I., Heijligers, M., Kleihorst, R.P., Danilin, A.,
An Embedded Low Power High Efficient Object Tracker for Surveillance Systems,
ICDSC07(372-378).
IEEE DOI Link 0709
BibRef

Litzenberger, M., Belbachir, A.N., Schon, P., Posch, C.,
Embedded Smart Camera for High Speed Vision,
ICDSC07(81-86).
IEEE DOI Link 0709
BibRef

Leon-Salas, W.D., Velipasalar, S., Schemm, N., Balkir, S.,
A Low-Cost, Tiled Embedded Smart Camera System for Computer Vision Applications,
ICDSC07(125-131).
IEEE DOI Link 0709
BibRef

Cornelis, N.[Nico], Van Gool, L.J.[Luc J.],
Fast scale invariant feature detection and matching on programmable graphics hardware,
CVGPU08(1-8).
IEEE DOI Link 0806
BibRef

Sugano, H.[Hiroki], Miyamoto, R.[Ryusuke],
A Real-Time Object Recognition System on Cell Broadband Engine,
PSIVT07(932-943).
Springer DOI Link 0712
Embedded processor (Sony playstation). 18fps for 8 targets. BibRef

Wang, B.J.[Bang-Ju], Zhang, H.G.[Huan-Guo], Wang, Z.Y.[Zhang-Yi], Wang, Y.H.[Yu-Hua],
Speeding Up Scalar Multiplication Using a New Signed Binary Representation for Integers,
MCAM07(277-285).
Springer DOI Link 0706
BibRef

Lai, M.C.[Ming-Che], Guo, J.J.[Jian-Jun], Lv, Y.S.[Ya-Suai], Dai, K.[Kui], Wang, Z.Y.[Zhi-Ying],
The Research of an Embedded Processor Element for Multimedia Domain,
MCAM07(267-276).
Springer DOI Link 0706
BibRef

Baumgartner, D.[Daniel], Rossler, P.[Peter], Kubinger, W.[Wilfried],
Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms,
EmbedCV07(1-8).
IEEE DOI Link 0706
BibRef

Gabriel, R.C., Gomes, J., de Mello, M.J.C., Haas, H.L., Petraglia, A.,
New Error Sensitivity Model for the Analog Hardware Implementation of Inner Products,
ICIP06(3333-3336). 0610

IEEE DOI Link BibRef

Rowe, A., Goode, A.G., Goel, D., and Nourbakhsh, I.,
CMUcam3: An Open Programmable Embedded Vision Sensor,
CMU-RI-TR-07-13, May, 2007.
WWW Version. BibRef 0705

Rowe, A., Rosenberg, C., Nourbakhsh, I.,
A Second Generation Low Cost Embedded Color Vision System,
EmbedCV05(III: 136-136).
IEEE DOI Link 0507
BibRef

Gong, M.L.[Ming-Lun], Langille, A.[Aaron], Gong, M.W.[Ming-Wei],
Real-Time Image Processing Using Graphics Hardware: A Performance Study,
ICIAR05(1217-1225).
Springer DOI Link 0509
BibRef

Jodoin, P.M.[Pierre-Marc], Mignotte, M.[Max], St-Amour, J.F.[Jean-François],
Markovian Energy-Based Computer Vision Algorithms on Graphics Hardware,
CIAP05(592-603).
Springer DOI Link 0509
BibRef

Kisacanin, B.[Branislav],
Integral Image Optimizations for Embedded Vision Applications,
Southwest08(181-184).
IEEE DOI Link 0803
BibRef
Earlier:
Examples of Low-Level Computer Vision on Media Processors,
EmbedCV05(III: 135-135).
IEEE DOI Link 0507
BibRef

Cabani, C.[Cristina], MacLean, W.J.[W. James],
A Proposed Pipelined-Architecture for FPGA-Based Affine-Invariant Feature Detectors,
EmbedCV06(121).
IEEE DOI Link 0609
BibRef

MacLean, W.J.,
An Evaluation of the Suitability of FPGAs for Embedded Vision Systems,
EmbedCV05(III: 131-131).
IEEE DOI Link 0507
BibRef

Stein, G.P., Rushinek, E., Hayun, G., Shashua, A.,
A Computer Vision System on a Chip: A case study from the automotive domain,
EmbedCV05(III: 130-130).
IEEE DOI Link 0507
BibRef

Chang, C.J.[Chi-Jeng], Wu, W.T.[Wu-Ting], Su, H.C.[Hui-Ching], Huang, Z.Y.[Zen-Yi], Li, H.Y.[Hsin-Yen],
ARM Based Microcontroller for Image Capturing in FPGA Design,
ISVC05(672-677).
Springer DOI Link 0512
BibRef

Bertalmio, M., Fort, P., Sanchez-Crespo, D.,
Real-time, accurate depth of field using anisotropic diffusion and programmable graphics cards,
3DPVT04(767-773).
IEEE Abstract. IEEE Top Reference. 0412
BibRef

Elouardi, A., Bouaziz, S., Dupret, A., Klein, J.O., Reynaud, R.,
On chip vision system architecture using a CMOS retina,
IVS04(206-211).
IEEE Abstract. IEEE Top Reference. 0411
BibRef

Woetzel, J., Koch, R.,
Multi-camera real-time depth estimation with discontinuity handling on PC graphics hardware,
ICPR04(I: 741-744).
IEEE DOI Link 0409
BibRef

Aziz, M., Boussakta, S., McLernon, D.C.,
Three-dimensional digital filtering algorithm for parallel DSP implementation,
ICIP03(II: 579-582).
IEEE Abstract. IEEE Top Reference. 0312
BibRef

Laffely, A., Liang, J.[Jian], Tessier, R., Burleson, W.,
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores,
ICIP03(III: 105-108).
IEEE Abstract. IEEE Top Reference. 0312
BibRef

Michell, J.A., Ruiz, G.A., Buron, A.M.,
Parallel-pipelined architecture for 2-D ICT VLSI implementation,
ICIP03(III: 89-92).
IEEE Abstract. IEEE Top Reference. 0312
BibRef

Lv, T., Ozer, B., Wolf, W.,
Exploiting parallelism in media processing using VLIW processor,
ICIP03(III: 97-100).
IEEE Abstract. IEEE Top Reference. 0312
BibRef

Lee, S.W.[Seong-Whan], Lee, S.W.[Sang-Woong], Jung, H.C.[Ho-Choul],
Real-Time Implementation of Face Recognition Algorithms on DSP Chip,
AVBPA03(294-301).
HTML Version. 0310
BibRef

van der Wal, G.S.[Gooitzen S.], Hsu, S.[Steve], Matei, B.C.[Bogdan C.],
Video Analysis using the Acadia I(TM) Single-Chip Vision System,
CVPR01(Demos 19-20). 0110
BibRef

McCurry, P., Morgan, F., Kilmartin, L.,
Xilinx FPGA Implementation of an Image Classifier for Object Detection Applications,
ICIP01(III: 346-349).
IEEE Abstract. IEEE Top Reference. 0108
BibRef

Vlassis, S., Fikos, G., Siskos, S.,
A Floating Gate CMOS Euclidean Distance Calculator and Its Application to Hand-written Digit Recognition,
ICIP01(III: 350-353).
IEEE Abstract. IEEE Top Reference. 0108
BibRef

McCanny, P., Masud, S., McCanny, J.,
An Efficient Architecture for the 2-d Biorthogonal Discrete Wavelet Transform,
ICIP01(III: 314-317).
IEEE Abstract. IEEE Top Reference. 0108
BibRef

Draper, B.A., Böhm, A.P.W.[A.P. Willem], Hammes, J., Najjar, W., Beveridge, J.R., Ross, C., Chawathe, M., Desai, M., Bins, J.,
Compiling SA-C Programs to FPGAs: Performance Results,
CVS01(220-235).
HTML Version. 0106
BibRef

Sudharsanan, S., Sriram, P., Frederickson, H., Gulati, A.,
Image and Video Processing Using MAJC 5200,
ICIP00(Vol III: 122-125).
IEEE Abstract. IEEE Top Reference. 0008
BibRef

Ooi, R., Hamamoto, T., Naemura, T., Aizawa, K.,
Pixel Independent Random Access Image Sensor for Real Time Image-based Rendering System,
ICIP01(II: 193-196).
IEEE Abstract. IEEE Top Reference. 0108
BibRef

Hamamoto, T.[Takayuki], Ooi, R.[Ryutaro], Ohtsuka, Y.[Yasuhiro], Aizawa, K.[Kiyoharu],
Real-Time Image Processing by Using Image Compression Sensor,
ICIP99(III:935-939).
IEEE Abstract. IEEE Top Reference. BibRef 9900

Peng, W.S.[Wen-Shiaw], Lee, C.Y.[Chen-Yi],
An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform,
ICIP99(II:754-758).
IEEE Abstract. IEEE Top Reference. BibRef 9900

Sousa, L.[Leonel],
Applying Conditional Processing to Design Low-Power Array Processors for Motion Estimation,
ICIP99(II:769-773).
IEEE Abstract. IEEE Top Reference. BibRef 9900

Ishikawa, M.[Masatoshi],
1ms VLSI Vision Chip System and Its Applications,
AFGR98(214-219).
IEEE DOI Link BibRef 9800

Sicard, G., Bouvier, G., Lelah, A.,
A Light Adaptive 4000 Pixels Analog Silicon Retina for Edge Extraction and Motion Detection,
MVA98(xx-yy). BibRef 9800

Benedetti, A.[Arrigo], Perona, P.[Pietro],
Real-Time 2-D Feature Detection on a Reconfigurable Computer,
CVPR98(586-593).
IEEE Abstract. IEEE Top Reference. BibRef 9800

Redford, J.,
A three Giga-op DSP chip for image processing,
ICIP98(III: 981-984).
IEEE DOI Link 9810
BibRef

Muramatsu, S., Kobayashi, Y., Araoka, M., Naoi, S., Kaneta, T., Hirose, K., Onizawa, S.,
Image processing LSI 'ISP-IV' based on local parallel architecture and its applications,
ICIP98(III: 1000-1004).
IEEE DOI Link 9810
BibRef

Gokstorp, M., Forchheimer, R.,
Smart vision sensors,
ICIP98(I: 479-482).
IEEE DOI Link 9810
BibRef

Spirig, T., Seitz, P., Vietze, O., Heitger, F., Kubler, O.,
Real-time 2D feature detection with low-level image processing algorithms on smart CCD/CMOS image sensors,
ICIP96(II: 1043-1046).
IEEE DOI Link 9610
BibRef

Chen, C.C.[Chih-Chin], Jen, C.W.[Chein-Wei],
A programmable concurrent video signal processor,
ICIP96(II: 1039-1042).
IEEE DOI Link 9610
BibRef

Sorel, Y.,
Real-time embedded image processing applications using the A3 methodology,
ICIP96(II: 145-148).
IEEE DOI Link 9610
BibRef

Ker, J.S.[Jar-Shone], Kuo, Y.H.[Yau-Hwang], Liu, B.D.[Bin-Da],
Design of a color reproduction neural network chip with on-chip learning capability,
ICIP96(II: 1023-1026).
IEEE DOI Link 9610
BibRef

Chen, C.L.[Chao-Lieh], Lee, C.S.[Chang-Shing], Kuo, Y.H.[Yau-Hwang],
Design of high speed weighted fuzzy mean filters with generic LR fuzzy cells,
ICIP96(II: 1027-1030).
IEEE DOI Link 9610
BibRef

Dallaire, S., Poussart, D., Tremblay, M.,
Low Level Segmentation Using CMOS Smart Hexagonal Image Sensor,
CAMP95(xx). BibRef 9500

Pechanek, G.G., Stojancic, M., Vassiliadis, S., Glossner, C.J.,
MFAST: a single chip highly parallel image processing architecture,
ICIP95(I: 69-72).
IEEE DOI Link 9510
BibRef

Muller, S.,
A new programmable VLSI architecture for histogram and statistics computation in different windows,
ICIP95(I: 73-76).
IEEE DOI Link 9510
BibRef

Potkonjak, M.,
Discrete-relaxation-based heuristic techniques for video algorithm/architecture matching and system level transformations,
ICIP95(I: 77-80).
IEEE DOI Link 9510
BibRef

Olstad, B., Steen, E., Halaas, A.,
Image filtering techniques and VLSI architectures for efficient data extraction in shell rendering,
ICIP95(II: 113-116).
IEEE DOI Link 9510
BibRef

Ranganathan, N., Venygopal, S.[Satish],
An Efficient VLSI Architecture for Template Matching Based on Moment Preserving Pattern Matching,
ICPR94(C:388-390).
IEEE DOI Link BibRef 9400

Tremblay, M., Savard, M., Poussart, D.,
Medium Level Scene Representation Using VLSI Smart Hexagonal Sensor with multi-resolution Edge Extraction Capability and Scale Space Integration Co-Processor,
CVPR94(632-637).
IEEE Abstract. IEEE Top Reference. BibRef 9400

Yates, R., Evans, S., Ivey, P.A.,
A 1.2 billion operations per second video signal processing chip,
ICIP94(III: 596-600).
IEEE DOI Link 9411
BibRef

Thacker, N.A., Courtney, P., Walker, S.N., Evans, S.J., Yates, R.B.,
Specification and design of a general purpose image processing chip,
ICPR94(C:268-273).
IEEE DOI Link 9410
BibRef

Stout, M.G., Salmon, L.G., Rudolph, G.L., Martinez, T.R.,
A VLSI implementation of a parallel, self-organizing learning model,
ICPR94(C:373-376).
IEEE DOI Link 9410
BibRef

Chen, S.[Sarit], Ginosar, R.,
Adaptive sensitivity CCD image sensor,
ICPR94(C:363-365).
IEEE DOI Link 9410
BibRef

Kabir, I., Hsieh, M., Donovan, W., Jabbi, A., Radke, W.,
Programmable image processing in a memory controller,
ICIP94(III: 672-677).
IEEE DOI Link 9411
BibRef

Tang, Y.Y., Cheng, X., Tao, L., Suen, C.Y., Talaat, M., Inglese, R.,
VLSI architecture for parallel concentration-contour approach,
ICPR92(IV:151-154).
IEEE DOI Link 9208
BibRef

Courtney, P.[Patrick], Thacker, N.A.[Neil A.], Brown, C.R.[Chris R.],
Hardware support for fast edge-based stereo,
ECCV92(902-906).
Springer DOI Link 9205
BibRef
And:
A Hardware Architecture for Image Rectification and Ground Plane Obstacle Detection,
ICPR92(IV:23-26).
IEEE DOI Link BibRef

Dron, L.,
System-level design of specialized VLSI hardware for computing relative orientation,
WACV92(128-135).
IEEE Abstract. IEEE Top Reference. 0403
BibRef

Patel, M., McCabe, P.A., Ranganathan, N.,
SIBA: a VLSI systolic array chip for image processing,
ICPR92(IV:15-18).
IEEE DOI Link 9208
BibRef

Sundaresan, V.K., Nichani, S., Ranganathan, N., Sankar, R.,
A VLSI hardware accelerator for dynamic time warping,
ICPR92(IV:27-30).
IEEE DOI Link 9208
BibRef

Botha, T.H.,
An analog CMOS programmable and configurable neural network,
ICPR92(IV:222-224).
IEEE DOI Link 9208
BibRef

Ishiyama, Y., Funaoka, C., Kubo, F., Takahashi, H., Tomita, F.,
Labeling board based on boundary tracking,
ICPR92(IV:34-38).
IEEE DOI Link 9208
Hardware implementation. BibRef

Fukushima, T.,
A survey of image processing LSIs in Japan,
ICPR90(II: 394-401).
IEEE DOI Link 9208
BibRef

Mao, W.D., Kung, S.Y.,
An object recognition system using stochastic knowledge source and VLSI parallel architecture,
ICPR90(I: 832-836).
IEEE DOI Link 9006
BibRef

Gijbels, T., Van Eycken, L., Oosterlinck, A., Note, S., Catthoor, F.,
An ASIC-architecture for VLSI-implementation of the RBN-algorithm,
ICPR90(II: 408-412).
IEEE DOI Link 9208
BibRef

Chen, K., Astrom, A., Danielsson, P.E.,
PASIC: a smart sensor for computer vision,
ICPR90(II: 286-291).
IEEE DOI Link 9208
BibRef

Tremblay, M., Poussart, D.,
MAR: an integrated system for focal plane edge tracking with parallel analog processing and built-in primitives for image acquisition and analysis,
ICPR90(II: 292-298).
IEEE DOI Link 9208
BibRef

Klein, J.C., Collange, F., Bilodeau, M.,
A bit plane architecture for an image analysis processor implemented with P.L.C.A. gate array,
ECCV90(33-49).
Springer DOI Link 9004
BibRef

Chapter on Implementations and Applications, Databases, QBIC, Video Analysis, Hardware and Software, Inspection continues in
Pipelined Processors and Algorithms .

Last update:Nov 16, 2009 at 19:35:14