Keith Price Bibliography Hardware and Architecture for Coding

5.4.13 Hardware and Architecture for Coding

Chapter Contents (Back)
Hardware. Architectures. Image Compression. Primarily single image coding issues. See also Motion and Video Coding: Hardware and Systems.

Wang, C.L.[Chin-Liang], Chen, C.Y.[Chang-Yu],
High-throughput VLSI architectures for the 1-D and 2-D discrete cosine transforms,
CirSysVideo(5), No. 1, February 1995, pp. 31-40.
IEEE Top Reference. 0206 BibRef

Hsia, S.C.[Shih-Chang], Liu, B.D.[Bin-Da], Yang, J.F.[Jar-Ferr], Bai, B.L.[Bor-Long],
VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor,
CirSysVideo(5), No. 5, October 1995, pp. 396-406.
IEEE Top Reference. 0206 BibRef

Venbrux, J., Yeh, P.S., Liu, M.N.,
A VLSI chip set for high-speed lossless data compression,
CirSysVideo(2), No. 4, December 1992, pp. 381-391.
IEEE Top Reference. 0206 BibRef

Balram, N., Moura, J.M.F.,
Noncausal Predictive Image Codec,
IP(5), No. 8, August 1996, pp. 1229-1242.
WWW Version. 9608 BibRef

Bull, D.R., Redmill, D.W.,
Optimization of Image-Coding Algorithms and Architectures Using Genetic Algorithms,
IndEle(43), No. 5, October 1996, pp. 549-558. 9610 BibRef

Redmill, D.W.[David W.], Bull, D.R.,
Non-linear perfect reconstruction filter banks for image coding,
ICIP96(I: 593-596).
WWW Version. BibRef 9600

Redmill, D.W.[David W.], Bull, D.R.,
Error Resilient Arithmetic Coding of Still Images,
ICIP96(II: 109-112).
WWW Version. BibRef 9600

Redmill, D.W., Kingsbury, N.G.,
Still image coding for noisy channels,
ICIP94(I: 95-99).
WWW Version. 9411 BibRef

Ancona, F., Rovetta, S., Zunino, R.,
An Efficient Technique for Implementing an Image Compression Neural Algorithm on Concurrent Multiprocessor,
EngAAI(10), No. 6, December 1997, pp. 573-580. 9807 BibRef

Masselos, K., Stouraitis, T., Goutis, C.E.,
Novel scheme for low-power classified vector quantisation image coding,
VISP(145), No. 6, December 1998, pp. 408. BibRef 9812

Masselos, K., Merakos, P., Stouraitis, T., Goutis, C.E.,
A Novel Algorithm for Low Power Image and Video Coding,
CirSysVideo(8), No. 3, June 1998, pp. 258-263.
IEEE Top Reference. 9806 BibRef

Acken, K.P., Irwin, M.J., Owens, R.M.,
A Parallel ASIC Architecture for Efficient Fractal Image-Coding,
VLSIVideo(19), No. 2, July 1998, pp. 97-113. 9809 BibRef

Kim, S., Sung, W.,
Fixed-Point Error Analysis and Word Length Optimization of 8 x 8 IDCT Architectures,
CirSysVideo(8), No. 8, December 1998, pp. 935.
IEEE Top Reference. BibRef 9812

Bi, M., Ong, S.H., Ang, Y.H.,
Integer-Modulated FIR Filter Banks for Image Compression,
CirSysVideo(8), No. 8, December 1998, pp. 923.
IEEE Top Reference. BibRef 9812

Jiang, J.M.[Jian-Min],
A novel parallel design of a codec for black and white image compression,
SP:IC(8), No. 5, July 1996, pp. 465-474.
WWW Version. BibRef 9607

Lim, H.G., Pang, K.K., Tan, T.K., Hall, S.C.,
A low complexity H.261-compatible software video decoder,
SP:IC(8), No. 1, January 1996, pp. 25-37.
WWW Version. BibRef 9601

Baskurt, A., Odet, C., Goutte, R.,
Image coding on the Phobos space probe,
SP:IC(6), No. 5, October 1994, pp. 479-484.
WWW Version. BibRef 9410

Chang, W.W., Wang, D.Y.,
Quality enhancement of sinusoidal transform vocoders,
VISP(145), No. 6, December 1998, pp. 379. BibRef 9812

Pang, T.C.J., Choy, C.S.O., Chan, C.F., Cham, W.K.,
A Self-Timed ICT Chip for Image Coding,
CirSysVideo(9), No. 6, September 1999, pp. 856. BibRef 9909

Kassim, A.A., Chua, K.S., Fong, F.K., Ranganath, S.,
DSP-based system for real-time video communications,
IJIST(10), No. 1, 1999, pp. 47-53. BibRef 9900

Zhao, D., Chan, Y.K., Gao, W.[Wen],
Low-complexity and low-memory entropy coder for image compression,
CirSysVideo(11), No. 10, October 2001, pp. 1140-1145.
IEEE Top Reference. 0110 BibRef

Tzou, K.H.,
High-order entropy coding for images,
CirSysVideo(2), No. 1, March 1992, pp. 87-89.
IEEE Top Reference. 0206 BibRef

Lei, S.M., Sun, M.T., Tzou, K.H.,
Design and hardware architecture of high-order conditional entropy coding for images,
CirSysVideo(2), No. 2, June 1992, pp. 176-186.
IEEE Top Reference. 0206 BibRef

Wei, B.W.Y., Meng, T.H.,
A parallel decoder of programmable Huffman codes,
CirSysVideo(5), No. 2, April 1995, pp. 175-178.
IEEE Top Reference. 0206 BibRef
Earlier:
A programmable parallel Huffman decoder,
ICIP94(III: 668-671).
WWW Version. 9411 BibRef

Wan, X.[Xia], Wang, Y.[Yiliang], Chen, W.H.,
Dynamic range analysis for the implementation of fast transform,
CirSysVideo(5), No. 2, April 1995, pp. 178-180.
IEEE Top Reference. 0206 BibRef

Ravasi, M., Tenze, L., Mattavelli, M.,
A scalable and programmable architecture for 2-d DWT decoding,
CirSysVideo(12), No. 8, August 2002, pp. 671-677.
IEEE Top Reference. 0208 BibRef

Wang, C.N., Yang, S.W., Liu, C.M., Chiang, T.,
A Hierarchical N-Queen Decimation Lattice and Hardware Architecture for Motion Estimation,
CirSysVideo(14), No. 4, April 2004, pp. 429-440.
IEEE Abstract. IEEE Top Reference. 0407 BibRef

Pastuszak, G.[Grzegorz],
A High-Performance Architecture for Embedded Block Coding in JPEG 2000,
CirSysVideo(15), No. 9, September 2005, pp. 1182-1191.
WWW Version. 0509 BibRef
Earlier:
Efficient Hardware Architecture for EBCOT in JPEG 2000 Using a Feedback Loop from the Rate Controller to the Bit-Plane Coder,
CIAP05(604-611).
WWW Version. 0509 BibRef

Corsonello, P., Perri, S., Staino, G., Lanuzza, M., Cocorullo, G.,
Low Bit Rate Image Compression Core for Onboard Space Applications,
CirSysVideo(16), No. 1, January 2006, pp. 114-128.
WWW Version. 0601 BibRef

Gupta, A.K., Nooshabadi, S., Taubman, D., Dyer, M.,
Realizing Low-Cost High-Throughput General-Purpose Block Encoder for JPEG2000,
CirSysVideo(16), No. 7, July 2006, pp. 843-858.
WWW Version. 0608 BibRef

Dyer, M.[Michael], Nooshabadi, S.[Saeid], Taubman, D.[David],
Analysis of Multiple Parallel Block Coding in JPEG2000,
ICIP07(V: 173-176).
WWW Version. 0709 BibRef

Li, Y., Bayoumi, M.,
A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000,
CirSysVideo(16), No. 9, September 2006, pp. 1153-1163.
WWW Version. 0610 BibRef

van Dyck, W.[Walter], Smodic, R.[Rene], Hufnagl, H.[Herbert], Berndorfer, T.[Thomas],
High-speed JPEG coder implementation for a smart camera,
RealTimeIP(1), No. 1, October 2006, pp. 63-68.
WWW Version. 0001 BibRef

Zhang, Y.Z.[Yi-Zhen], Xu, C.[Chao], Wang, W.T., Chen, L.B.,
Performance Analysis and Architecture Design for Parallel EBCOT Encoder of JPEG2000,
CirSysVideo(17), No. 10, October 2007, pp. 1336-1347.
WWW Version. 0711 BibRef

Zhang, Y.Z.[Yi-Zhen], Xu, C.[Chao],
Analysis and Effective Parallel Technique for Rate-Distortion Optimization in JPEG2000,
ICIP06(2465-2468). 0610
WWW Version. BibRef
Earlier:
Analysis and High Performance Parallel Architecture Design for EBCOT in JPEG2000,
ICIP05(III: 996-999).
WWW Version. 0512 BibRef

Kurdthongmee, W.,
A novel Kohonen SOM-based image compression architecture suitable for moderate density FPGAs,
IVC(26), No. 8, 1 August 2008, pp. 1094-1105.
WWW Version. 0806Image quantization; Image compression; FPGA-based implementation; Kohonen self-organizing map BibRef

Duarte, M.F.[Marco F.], Davenport, M.A.[Mark A.], Wakin, M.B.[Michael B.], Laska, J.N.[Jason N.], Takhar, D.[Dharmpal], Kelly, K.F.[Kevin F.], Baraniuk, R.G.[Richard G.],
Multiscale Random Projections for Compressive Classification,
ICIP07(VI: 161-164).
WWW Version. 0709 BibRef

Wakin, M.B., Laska, J.N., Duarte, M.F., Baron, D., Sarvotham, S., Takhar, D., Kelly, K.F., Baraniuk, R.G.,
An Architecture for Compressive Imaging,
ICIP06(1273-1276). 0610
WWW Version. BibRef