Yang, K.M.[Kun-Min],
Legall, D.J.[Didier J.],
Hardware design of a motion video decoder for 1-1.5 Mbps rate
applications,
SP:IC(2), No. 2, August 1990, pp. 117-126.
WWW Version.
0001Modular hardware design; evaluation of hardware complexity;
compatibility with other coding algorithm
BibRef
de Lameillieure, J.L.P.[Jan L.P.],
Bruyland, I.[Ignace],
Single stage 280 Mbit/s coding of HDTV using HDPCM with a vector
quantizer based on masking functions,
SP:IC(2), No. 3, October 1990, pp. 279-289.
WWW Version.
0001
BibRef
Hamilton, E.R.[Eric R.],
Douglas, J.L.[John L.],
Widergren, J.B.[Jeffrey B.],
Computer-based video compression system,
US_Patent4,897,717, 01/30/1990.
HTML Version.
BibRef
9001
Adolph, D.[Dirk],
Buschmann, R.[Ralf],
1.15 Mbit/s coding of video signals including global motion
compensation,
SP:IC(3), No. 2-3, June 1991, pp. 259-274.
WWW Version.
0001
BibRef
Brofferio, S.,
Mastronardi, G.,
Rampa, V.,
A migrating data-driven architecture for multidimensional signal
processing,
SP:IC(3), No. 2-3, June 1991, pp. 249-257.
WWW Version.
0001
BibRef
Sawada, K.[Katsutoshi],
Yashima, Y.[Yoshiyuki],
Sakai, H.[Hiroshi],
An HDTV bit-rate reduction codec at the STM-1 rate of SDH,
SP:IC(4), No. 4-5, August 1992, pp. 345-358.
WWW Version.
0001HDTV; bit-rate reduction; DCT; STM-1
BibRef
Matsumoto, S.[Shuichi],
Murakami, H.[Hitomi],
120/140 Mbit/s portable HDTV codec and its transmission performance in
a field trial via INTELSAT satellite,
SP:IC(4), No. 4-5, August 1992, pp. 359-377.
WWW Version.
0001HDTV; intrafield DPCM; noise shaping; field trial; BER; link budget
BibRef
Matsumoto, S.[Shuichi],
Murakami, H.[Hitomi],
Murakami, H.[Hitomi],
Yamamoto, H.[Hideo],
Adaptive predictive coding system for television signals,
US_Patent4,546,386, 10/08/1985.
HTML Version.
BibRef
8510
Earlier:
Inter-frame adaptive prediction system for television signals,
US_Patent4,437,119, 03/13/1984.
HTML Version.
BibRef
Ohtsuka, Y.[Yoshimichi],
Nakasu, E.[Eisuke],
Shishikui, Y.[Yoshiaki],
Imaizumi, H.[Hiroyuki],
Nakanishi, H.[Hiroshi],
Development of 135 Mbit/s HDTV codec,
SP:IC(4), No. 4-5, August 1992, pp. 379-387.
WWW Version.
0001HDTV; DCT; motion compensation; B2 code; CCIR Rec.723
BibRef
Okubo, S.[Sakae],
Wada, M.[Masahiro],
Carr, M.D.[Mike D.],
Tabatabai, A.J.[Ali J.],
Hardware trials for verifying recommendation H.261 on p*64 kbit/s video
codec,
SP:IC(3), No. 1, February 1991, pp. 71-78.
WWW Version.
0001Visual telephone service; Recommendation H.261
BibRef
Watanabe, H.[Hiroshi],
Suzuki, Y.[Yutaka],
64 kbit/s Video coding algorithm using adaptive gain/shape vector
quantization,
SP:IC(1), No. 2, October 1990, pp. 87-102.
WWW Version.
0001High efficiency video coding; hybrid coding; vector quantization; tree search codebook; gain/shape vector quantization; motion compensation; conditional replenishment; videoconferencing; videophone; video codec; ISDN terminal
BibRef
Grotz, K.[Karlheinz],
Mayer, J.U.[Joerg U.],
Suessmeier, G.K.[Georg K.],
A 64 kbit/s Videophone codec with forward analysis and control,
SP:IC(1), No. 2, October 1990, pp. 103-115.
WWW Version.
0001Displacement estimation by gradient method; motion compensation with subpel aaccuracy; noise adaptation; forward control
BibRef
Hoek, C.[Cornelis],
Heiss, R.[Rainer],
Mueller, D.[Detlef],
An array processor approach for low bit rate video coding,
SP:IC(1), No. 2, October 1990, pp. 213-223.
WWW Version.
0001Hybrid codec; videocoding; array processor; SIMD
BibRef
Balestri, M.,
Rinaudo, A.,
A general architecture of video codec for real time communication at 64
kbit/s,
SP:IC(1), No. 2, October 1990, pp. 239-243.
WWW Version.
0001Photovideotex; videophone; video coding; parallel processing
BibRef
Chen, L.G.[Liang-Gee],
Liu, Y.C.[Yuan-Chen],
A high quality MC-OBTC Codec for video signal processing,
CirSysVideo(4), No. 1, February 1994, pp. 92-98.
IEEE Top Reference.
0206
BibRef
Chang, S.F.,
Messerschmitt, D.G.,
Designing high-throughput VLC decoder. I. Concurrent VLSI architectures,
CirSysVideo(2), No. 2, June 1992, pp. 187-196.
IEEE Top Reference.
0206
BibRef
Lin, H.D.,
Messerschmitt, D.G.,
Designing a high-throughput VLC decoder. II. Parallel decoding methods,
CirSysVideo(2), No. 2, June 1992, pp. 197-206.
IEEE Top Reference.
0206
BibRef
Frimout, E.D.,
Driessen, I.N.,
Deprettere, E.F.,
Parallel architecture for a pel-recursive motion estimation algorithm,
CirSysVideo(2), No. 2, June 1992, pp. 159-168.
IEEE Top Reference.
0206
BibRef
Jeschke, H.,
Gaedke, K.,
Pirsch, P.,
Multiprocessor performance for real-time processing of video coding
applications,
CirSysVideo(2), No. 2, June 1992, pp. 221-230.
IEEE Top Reference.
0206
BibRef
Villasenor, J.D.,
Jones, C.,
Schoner, B.,
Video communications using rapidly reconfigurable hardware,
CirSysVideo(5), No. 6, December 1995, pp. 565-567.
IEEE Top Reference.
0206
BibRef
Tsern, E.K.,
Meng, T.H.,
A Low-Power Video-Rate Pyramid VQ Decoder,
SolidCir(31), No. 11, November 1996, pp. 1789-1794.
9611
BibRef
Lin, H.D.,
Anesko, A.,
Petryna, B.,
A 14-GOPs Programmable Motion Estimator for H.26X Video Coding,
SolidCir(31), No. 11, November 1996, pp. 1742-1750.
9611
BibRef
Huang, H.C.,
Wu, J.L.,
New-Generation of Real-Time Software-Based Video Coder:
Popular-Video-Coder-II (PVC-II),
Consumer(42), No. 4, November 1996, pp. 963-973.
9701
BibRef
Hsiau, D.Y.,
Wu, J.L.,
Real Time PC Based Software Implementation of H.261 Video Codec,
Consumer(43), No. 4, November 1997, pp. 1234-1244.
9801
BibRef
Schuster, G.M.,
Katsaggelos, A.K.,
A Video Compression Scheme with Optimal Bit Allocation
Among Segmentation, Motion, and Residual Error,
IP(6), No. 11, November 1997, pp. 1487-1502.
WWW Version.
9710
BibRef
Wang, H.H.[Hao-Hong],
Schuster, G.M.,
Katsaggelos, A.K.,
Object-based video compression scheme with optimal bit allocation among
shape, motion and texture,
ICIP03(III: 785-788).
IEEE Abstract. IEEE Top Reference.
0312
BibRef
Schuster, G.M.,
Katsaggelos, A.K.,
An Optimal Quadtree-based Motion Estimation and
Motion-compensated Interpolation Scheme for Video Compression,
IP(7), No. 11, November 1998, pp. 1505-1523.
WWW Version.
BibRef
9811
Lu, Y.,
Yong, Z.,
Yao, Q.D.,
Hierarchical Motion Estimation Algorithms with Especially
Low Hardware Costs,
Consumer(44), No. 1, February 1998, pp. 125-129.
9804
BibRef
Liu, P.C.,
Chang, W.T.,
Shen, W.Z.,
Combinative Motion Estimation Algorithm and the
Corresponding Architecture for Complex Motion Phenomenon,
Consumer(44), No. 1, February 1998, pp. 108-116.
9804
BibRef
Kweh, T.H.,
Eryurtlu, F.,
Kondoz, A.M.,
Closed Loop Motion Compensation for Video Coding Standards,
VISP(144), No. 4, August 1997, pp. 227-232.
9806
BibRef
Boo, K.J.,
Bose, N.K.,
A Motion Compensated Spatiotemporal Filter for
Image Sequences with Signal Dependent Noise,
CirSysVideo(8), No. 3, June 1998, pp. 287-298.
IEEE Top Reference.
9806
BibRef
Schutten, R.J.,
de Haan, G.,
Real-Time 2-3 Pull-Down Elimination Applying
Motion Estimation/Compensation in a Programmable Device,
Consumer(44), No. 3, August 1998, pp. 930-938.
9810
BibRef
Chiu, Y.J.,
Berger, T.,
Software-Only Videocodec Using Pixelwise Conditional Differential
Replenishment and Perceptual Enhancements,
CirSysVideo(9), No. 4, April 1999, pp. 438.
IEEE Top Reference.
BibRef
9904
Huang, H.C.[Ho-Chao],
Wu, J.L.[Ja-Ling],
Real-time software-based moving picture coding (SBMPC) system,
SP:IC(6), No. 2, May 1994, pp. 173-187.
WWW Version.
BibRef
9405
Choi, S.H.,
Park, K.T.,
High-speed moving picture coding using adaptively load balanced
multiprocessor system,
SP:IC(8), No. 2, March 1996, pp. 113-130.
WWW Version.
BibRef
9603
Choi, J.,
Distortion Policy of Buffer-Constrained Rate Control for Real-Time VBR
Coders,
IP(8), No. 4, April 1999, pp. 537-547.
WWW Version.
BibRef
9904
Charot, F.,
LeFol, G.,
Lemonnier, P.,
Wagner, C.,
Barzic, R.,
Bouville, C.,
Toward Hardware Building Blocks for Software-Only Real-Time Video
Processing: The MOVIE Approach,
CirSysVideo(9), No. 6, September 1999, pp. 882.
IEEE Top Reference.
BibRef
9909
Li, J.H.,
Ling, N.,
Architecture and Bus-Arbitration Schemes for MPEG-2 Video Decoder,
CirSysVideo(9), No. 5, August 1999, pp. 727.
IEEE Top Reference.
BibRef
9908
Kim, C.S.,
Kim, R.C.,
Lee, S.U.,
An Error Detection and Recovery Algorithm for Compressed Video Signal
Using Source Level Redundancy,
IP(9), No. 2, February 2000, pp. 209-219.
WWW Version.
0003
BibRef
Cheung, G.,
Zakhor, A.[Avideh],
Bit Allocation for Joint Source/Channel Coding of Scalable Video,
IP(9), No. 3, March 2000, pp. 340-356.
WWW Version.
0003
BibRef
Earlier:
Joint Source/Channel Coding of Scalable Video over Noisy Channels,
ICIP96(III: 767-770).
WWW Version.
9610Wireless
BibRef
Lentola, L.,
Cortelazzo, G.M.,
Malavasi, E.,
Baschirotto, A.,
Design of SC Filters for Video Applications,
CirSysVideo(10), No. 1, February 2000, pp. 14.
IEEE Top Reference.
0003
BibRef
Miyake, J.,
Urano, M.,
Inoue, G.,
Yano, J.,
Tsubata, S.,
Nishiyama, T.,
Yamaguchi, S.,
Architecture of 23GOPs Video Signal Processor with
Programmable Systolic Array,
CirSysSignal(45), No. 9, September 1998, pp. 1272-1278.
9809
BibRef
Oh, S.H.,
Han, S.H.,
Kang, B.,
Lee, M.K.,
An ASIC Implementation of an Optimized Digital Video Encoder,
Consumer(44), No. 3, August 1998, pp. 1097-1102.
9810
BibRef
Dutta, S.,
O'Connor, K.J.,
Wolf, W.,
Wolfe, A.,
A Design Study of a 0.25-Mu-M Video Signal Processor,
CirSysVideo(8), No. 4, August 1998, pp. 501-519.
IEEE Top Reference.
9809
BibRef
Mattavelli, M.,
Brunetton, S.,
Implementing Real-Time Video Decoding On Multimedia Processors by
Complexity Prediction Techniques,
Consumer(44), No. 3, August 1998, pp. 760-767.
9810
BibRef
Yu, G.S.,
Liu, M.M.K.,
Marcellin, M.W.,
POCS-Based Error Concealment for Packet Video
Using Multiframe Overlap Information,
CirSysVideo(8), No. 4, August 1998, pp. 422-434.
IEEE Top Reference.
9809
BibRef
Jeon, J.H.,
Park, Y.S.,
Park, H.W.,
A Fast Variable-Length Decoder Using Plane Separation,
CirSysVideo(10), No. 5, August 2000, pp. 806-812.
IEEE Top Reference.
0008
BibRef
Lee, C.S.[Chul Soo],
Park, J.[JoonHong],
Yoon, D.[DooSoo],
Jeon, J.[JaeHo],
Park, H.W.[Hyun-Wook],
Yeo, J.H.[Ji Hee],
Lee, J.H.[Jong Hwa],
A real-time encoding and decoding system for nonlinear HDTV editor,
IJIST(11), No. 2, 2000, pp. 152-157.
0008
BibRef
Lee, W.S.,
Pickering, M.R.,
Frater, M.R.,
Arnold, J.F.,
A Robust Codec for Transmission of Very Low Bit-Rate Video over
Channels with Bursty Errors,
CirSysVideo(10), No. 8, December 2000, pp. 1403-1412.
IEEE Top Reference.
0012
BibRef
Leung, K.K.,
Yung, N.H.C.,
Cheung, P.Y.S.,
Parallelization Methodology for Video Coding:
An Implementation on the TMS320C80,
CirSysVideo(10), No. 8, December 2000, pp. 1413-1425.
IEEE Top Reference.
0012
BibRef
Shieh, B.J.,
Lee, Y.S.,
Lee, C.Y.,
A High-Throughput Memory-Based VLC Decoder with Codeword Boundary
Prediction,
CirSysVideo(10), No. 8, December 2000, pp. 1514-1521.
IEEE Top Reference.
0012
BibRef
Yung, N.H.C.,
Leung, K.K.,
Spatial and Temporal Data Parallelization of the H.261 Video Coding
Algorithm,
CirSysVideo(11), No. 1, January 2001, pp. 91-104.
IEEE Top Reference.
0101
BibRef
Shieh, B.J.[Bai-Jue],
Lee, Y.S.[Yew-San],
Lee, C.Y.[Chen-Yi],
A new approach of group-based VLC codec system with full table
programmability,
CirSysVideo(11), No. 2, February 2001, pp. 210-221.
IEEE Top Reference.
0104
BibRef
Regunathan, S.L.[Shankar L.],
Zhang, R.[Rui],
Rose, K.[Kenneth],
Scalable video coding with robust mode selection,
SP:IC(16), No. 8, May 2001, pp. 725-732.
WWW Version.
0106
BibRef
Zhang, R.,
Regunathan, S.L.,
Rose, K.,
Prescient Mode Selection for Robust Video Coding,
ICIP01(I: 974-977).
IEEE Abstract. IEEE Top Reference.
0108
BibRef
Zhang, R.,
Regunathan, S.L.,
Rose, K.,
Switched Error Concealment and Robust Coding Decisions in Scalable
Video Coding,
ICIP00(Vol III: 380-383).
IEEE Abstract. IEEE Top Reference.
0008
BibRef
Bystrom, M.,
Kaiser, S.,
Kopansky, A.,
Soft source decoding with applications,
CirSysVideo(11), No. 10, October 2001, pp. 1108-1120.
IEEE Top Reference.
0110
BibRef
Kim, H.[Hansoo],
Park, I.C.[In-Cheol],
High-performance and low-power memory-interface architecture for video
processing applications,
CirSysVideo(11), No. 11, November 2001, pp. 1160-1170.
IEEE Top Reference.
0111
BibRef
Chen, W.S.[Wen-Shiung],
Peng, Y.Y.[Yuan-Yu],
Chang, Y.T.[Yung-Tsang],
Wang, J.T.[Jen-Tse],
Design and implementation of real-time software-based H.261 video codec,
IJIST(12), No. 2, 2002, pp. 73-83.
WWW Version.
0205
BibRef
Wei, S.W.,
Wei, C.H.,
A high-speed real-time binary BCH decoder,
CirSysVideo(3), No. 2, April 1993, pp. 138-147.
IEEE Top Reference.
0206
BibRef
Luo, J.H.[Jeng-Hung],
Wang, C.N.[Chung-Neng],
Chiang, T.[Tihao],
A novel all-binary motion estimation (ABME) with optimized hardware
architectures,
CirSysVideo(12), No. 8, August 2002, pp. 700-712.
IEEE Top Reference.
0208
BibRef
Panusopone, K.,
Baylon, D.M.,
An analysis and efficient implementation of half-pel motion estimation,
CirSysVideo(12), No. 8, August 2002, pp. 724-729.
IEEE Top Reference.
0208
BibRef
Tung, Y.S.[Yi-Shin],
Wu, J.L.[Ja-Ling],
Hsiao, P.K.[Po-Kang],
Huang, K.L.[Kan-Li],
An efficient streaming and decoding architecture for stored fgs video,
CirSysVideo(12), No. 8, August 2002, pp. 730-735.
IEEE Top Reference.
0208
BibRef
Li, Z.G.,
Zhu, C.,
Ling, N.,
Yang, X.K.,
Feng, G.N.,
Wu, S.,
Pan, F.,
A unified architecture for real-time video-coding systems,
CirSysVideo(13), No. 6, June 2003, pp. 472-487.
IEEE Abstract. IEEE Top Reference.
0307
BibRef
Caetano, R.[Rogério],
da Silva, E.A.B.[Eduardo A.B.],
A bit allocation scheme for a class of embedded wavelet video encoders,
JVCIR(14), No. 2, June 2003, pp. 136-149.
WWW Version.
0306
BibRef
Zhao, Y.F.[Ya-Fan],
Richardson, I.E.G.[Iain E.G.],
Macroblock classification for complexity management of video encoders,
SP:IC(18), No. 9, October 2003, pp. 801-811.
WWW Version.
0310
BibRef
Earlier: A2, A1:
Video encoder complexity reduction by estimating skip mode distortion,
ICIP04(I: 103-106).
WWW Version.
0505
BibRef
Tatas, K.,
Dasygenis, M.,
Kroupis, N.,
Argyriou, A.[Antonios],
Soudris, D.,
Thanailakis, A.,
Data memory power optimization and performance exploration of embedded
systems for implementing motion estimation algorithms,
RealTimeImg(9), No. 6, December 2003, pp. 371-386.
WWW Version.
0401
BibRef
Yen, J.C.,
Chang, F.J.,
Chang, S.[Shyang],
A new architecture for motion-compensated image coding,
PR(25), No. 4, April 1992, pp. 357-366.
WWW Version.
0401
BibRef
Li, T.[Tang],
Computation reduction for standard-based video encoders based on the
energy preservation property of DCT,
SP:IC(19), No. 5, May 2004, pp. 457-464.
WWW Version.
0405
BibRef
Tanskanen, J.K.,
Sihvo, T.,
Niittylahti, J.,
Byte and Modulo Addressable Parallel Memory Architecture for Video
Coding,
CirSysVideo(14), No. 11, November 2004, pp. 1270-1276.
IEEE Abstract. IEEE Top Reference.
0411
BibRef
Choi, B.D.[Byeong-Doo],
Choi, K.S.[Kang-Sun],
Hwang, M.C.[Min-Cheol],
Cho, J.K.[Jun-Ki],
Ko, S.J.[Sung-Jea],
Real-time DSP implementation of motion:
JPEG2000 using overlapped block transferring and parallel-pass methods,
RealTimeImg(10), No. 5, October 2004, pp. 277-284.
WWW Version.
0501
BibRef
Choi, B.D.[Byeong-Doo],
Han, J.W.[Jong-Woo],
Jung, S.W.[Seung-Won],
Nam, J.H.[Ju-Hun],
Ko, S.J.[Sung-Jea],
Overlapped Block Motion Compensation Based on Irregular Grid,
ICIP06(1085-1088).
0610
WWW Version.
BibRef
Feng, W.[Wei],
Kassim, A.A.[Ashraf A.],
Tham, C.K.[Chen-Khong],
A scalable video codec for layered video streaming,
RealTimeImg(10), No. 5, October 2004, pp. 297-305.
WWW Version.
0501
BibRef
Yang, C.L.,
Tseng, H.W.,
Ho, C.C.,
Wu, J.L.,
Software-Controlled Cache Architecture for Energy Efficiency,
CirSysVideo(15), No. 5, May 2005, pp. 634-644.
IEEE Abstract. IEEE Top Reference.
0505
BibRef
Chen, T.F.,
Hsu, C.M.,
Wu, S.R.,
Flexible Heterogeneous Multicore Architectures for Versatile Media
Processing Via Customized Long Instruction Words,
CirSysVideo(15), No. 5, May 2005, pp. 659-672.
IEEE Abstract. IEEE Top Reference.
0505
BibRef
Ravasi, M.,
Mattavelli, M.,
High-Abstraction Level Complexity Analysis and Memory Architecture
Simulations of Multimedia Algorithms,
CirSysVideo(15), No. 5, May 2005, pp. 673-684.
IEEE Abstract. IEEE Top Reference.
0505
BibRef
Shen, G.,
Gao, G.P.,
Li, S.,
Shum, H.Y.,
Zhang, Y.Q.,
Accelerate Video Decoding With Generic GPU,
CirSysVideo(15), No. 5, May 2005, pp. 685-693.
IEEE Abstract. IEEE Top Reference.
0505
BibRef
Guevorkian, D.,
Launiainen, A.,
Lappalainen, V.,
Liuha, P.,
Punkka, K.,
A Method for Designing High-Radix Multiplier-Based Processing Units for
Multimedia Applications,
CirSysVideo(15), No. 5, May 2005, pp. 716-725.
IEEE Abstract. IEEE Top Reference.
0505
BibRef
Wu, C.B.,
Yao, C.Y.,
Liu, B.D.,
Yang, J.F.,
DCT-Based Adaptive Thresholding Algorithm for Binary Motion Estimation,
CirSysVideo(15), No. 5, May 2005, pp. 694-703.
IEEE Abstract. IEEE Top Reference.
0505
BibRef
Li, P.,
Veeravalli, B.,
Kassim, A.A.,
Design and Implementation of Parallel Video Encoding Strategies Using
Divisible Load Analysis,
CirSysVideo(15), No. 9, September 2005, pp. 1098-1112.
WWW Version.
0509
BibRef
Kwon, D.N.,
Driessen, P.F.,
Basso, A.,
Agathoklis, P.,
Performance and Computational Complexity Optimization in Configurable
Hybrid Video Coding System,
CirSysVideo(16), No. 1, January 2006, pp. 31-42.
WWW Version.
0601
BibRef
Balam, S.,
Schonfeld, D.,
Associative processors for video coding applications,
CirSysVideo(16), No. 2, February 2006, pp. 241-250.
WWW Version.
0604
BibRef
Chen, K.H.,
Guo, J.I.,
Wang, J.S.,
A High-Performance Direct 2-D Transform Coding IP Design for MPEG-4
AVC/H.264,
CirSysVideo(16), No. 4, April 2006, pp. 472-483.
WWW Version.
0605
BibRef
Chen, C.Y.,
Huang, C.T.,
Chen, Y.H.,
Chen, L.G.,
Level C+ Data Reuse Scheme for Motion Estimation With Corresponding
Coding Orders,
CirSysVideo(16), No. 4, April 2006, pp. 553-558.
WWW Version.
0605
BibRef
Sayed, M.,
Badawy, W.,
An Affine-Based Algorithm and SIMD Architecture for Video Compression
With Low Bit-Rate Applications,
CirSysVideo(16), No. 4, April 2006, pp. 457-471.
WWW Version.
0605
BibRef
Ku, C.W.,
Cheng, C.C.,
Yu, G.S.,
Tsai, M.C.,
Chang, T.S.,
A High-Definition H.264/AVC Intra-Frame Codec IP for Digital Video and
Still Camera Applications,
CirSysVideo(16), No. 8, August 2006, pp. 917-928.
WWW Version.
0609
BibRef
Akil, M.,
Perroton, L.,
Grandpierre, T.,
FPGA-based architecture for hardware compression/decompression of wide
format images,
RealTimeIP(1), No. 2, December 2006, pp. 163-170.
WWW Version.
0001
BibRef
Amer, I.[Ihab],
Badawy, W.[Wael],
Jullien, G.[Graham],
A proposed hardware reference model for spatial transformation and
quantization in H.264,
JVCIR(17), No. 2, April 2006, pp. 533-552.
WWW Version.
0711H.264; Advanced video coding; DCT; Hadamard; Hardware; VLSI;
FPGA; ASIC; Transform; Quantization; Video coding
BibRef
Chang, Y.W.[Yu-Wei],
Cheng, C.C.[Chih-Chi],
Chen, C.C.[Chun-Chia],
Fang, H.C.[Hung-Chi],
Chen, L.G.[Liang-Gee],
124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile
Memory,
CirSysVideo(17), No. 4, April 2007, pp. 398-406.
WWW Version.
0705
BibRef
François, E.,
Viéron, J.,
Bottreau, V.,
Interlaced Coding in SVC,
CirSysVideo(17), No. 9, September 2007, pp. 1136-1148.
WWW Version.
0711Scalable Video Codec
BibRef
Chen, Y.K.[Yen-Kuang],
Li, E.Q.[Eric Q.],
Zhou, X.S.[Xiao-Song],
Ge, S.[Steven],
Implementation of H.264 encoder and decoder on personal computers,
JVCIR(17), No. 2, April 2006, pp. 509-532.
WWW Version.
0711H.264; Video codec; Multimedia; MMX/SSE Technologies; SIMD;
Hyper-Threading Technology; Multi-threading
BibRef
Ren, J.F.[Jian-Feng],
Kehtarnavaz, N.[Nasser],
Budagavi, M.[Madhukar],
A fast feature-assisted adaptive early termination approach for
multiple reference frames motion estimation in H.264,
RealTimeIP(3), No. 1-2, March 2008, pp. xx-yy.
WWW Version.
0804
BibRef
Babionitakis, K.,
Doumenis, G.,
Georgakarakos, G.,
Lentaris, G.,
Nakos, K.,
Reisis, D.,
Sifnaios, I.,
Vlassopoulos, N.,
A real-time H.264/AVC VLSI encoder architecture,
RealTimeIP(3), No. 1-2, March 2008, pp. xx-yy.
WWW Version.
0804
BibRef
Tseng, P.,
Chang, Y.,
Huang, Y.,
Fang, H.,
Huang, C.,
Chen, L.,
Advances in Hardware Architectures for Image and Video Coding:
A Survey,
PIEEE(93), No. 1, January 2005, pp. 184-197.
WWW Version.
0501
Survey, Compression.
BibRef
Martínez, J.L.,
Fernando, W.A.C.,
Weerakkody, W.A.R.J.,
Oliver, J.,
López, O.,
Martinez, M.,
Pérez, M.,
Cuenca, P.,
Quiles, F.,
Low-Complexity TTCM Based Distributed Video Coding Architecture,
PSIVT07(841-852).
WWW Version.
0712
BibRef
Zatt, B.[Bruno],
Ferreira, V.[Valter],
Agostini, L.[Luciano],
Wagner, F.R.[Flávio R.],
Susin, A.[Altamiro],
Bampi, S.[Sergio],
Motion Compensation Hardware Accelerator Architecture for H.264/AVC,
PSIVT07(24-35).
WWW Version.
0712
BibRef
Akyol, E.[Emrah],
van der Schaar, M.[Mihaela],
Buffer Constrained Proactive Dynamic Voltage Scaling for Video Decoding
Systems,
ICIP07(VI: 477-480).
WWW Version.
0709
BibRef
Sakaida, S.[Shinichi],
Nakajima, N.[Nao],
Ichigaya, A.[Atsuro],
Kurozumi, M.[Masaaki],
Iguchi, K.[Kazuhisa],
Nishida, Y.[Yukihiro],
Nakasu, E.[Eisuke],
Gohshi, S.[Seiichi],
The Super Hi-Vision Codec,
ICIP07(I: 21-24).
WWW Version.
0709
BibRef
Koskinen, L.[Lauri],
Marku, J.[Joona],
Paasio, A.[Ari],
Halonen, K.[Kari],
Architecture for Analog Variable Block-Size Motion Estimation,
ICIP07(II: 493-496).
WWW Version.
0709
BibRef
Kim, H.[Haksoo],
Kim, M.[Manbae],
The Design of Single Encoder and Decoder for Multi-view Video,
PSIVT06(732-741).
WWW Version.
0612
BibRef
Pyen, S.M.[Seung-Man],
Min, K.Y.[Kyeong-Yuk],
Chong, J.W.[Jong-Wha],
Goto, S.[Satoshi],
An Efficient Hardware Architecture for Full-Search Variable Block Size
Motion Estimation in H.264/AVC,
ISVC06(II: 554-563).
WWW Version.
0611
BibRef
Ou, C.M.[Chien-Min],
Roan, H.C.[Huang-Chun],
Hwang, W.J.[Wen-Jyi],
Fractional Full-Search Motion Estimation VLSI Architecture for
H.264/AVC,
PSIVT06(861-868).
WWW Version.
0612
BibRef
Lu, X.,
Manduchi, R.,
Fast Image Motion Computation on an Embedded Computer,
EmbedCV06(120).
WWW Version.
0609
BibRef
Tripathi, S.[Shikha],
Vikas, R.,
Jain, R.C.,
An Efficient Real Time Low Bit Rate Video Codec,
ACCV06(I:500-508).
WWW Version.
0601
BibRef
Yang, Z.[Zhi],
Zhang, H.[Haixiang],
Bu, J.[Jiajun],
Chen, C.[Chun],
Complexity-Controllable Motion Estimation for Real-Time Video Encoder,
ICIAR05(1266-1273).
WWW Version.
0509
BibRef
Molino, A.,
Vacca, F.,
Masera, G.,
Optimized Cordic Core for Frequency-Domain Motion Estimation,
ICIP05(III: 1072-1075).
WWW Version.
0512Compute the phase difference, use in CODEC.
BibRef
Dubois, J.,
Mattavelli, M.,
Pierrefeu, L.,
Miteran, J.,
Configurable Motion-Estimation Hardware Accelerator Module for the
MPEG-4 Reference Hardware Description Platform,
ICIP05(III: 1040-1043).
WWW Version.
0512
BibRef
López, M.F.,
Rodríguez, S.G.,
Ortiz, J.P.,
Dana, J.M.,
Ruiz, V.G.,
García, I.,
FSVC: A New Fully Scalable Video Codec,
CAIP05(171).
WWW Version.
0509
BibRef
Ishwar, P.,
Ramchandran, K.,
On decoder-latency versus performance tradeoffs in differential
predictive coding,
ICIP04(II: 1097-1100).
WWW Version.
0505
BibRef
Liu, T.M.[Tsu-Ming],
Lee, C.Y.[Chen-Yi],
A low-complexity soft VLC decoder using performance modeling,
ICIP04(V: 3233-3236).
WWW Version.
0505
BibRef
Xie, G.[Gui],
Shen, H.[Hong],
A highly scalable speck image coder,
ICIP04(II: 1297-1300).
WWW Version.
0505
BibRef
Lu, L.[Ligang],
Sheinin, V.,
Rate and decoding power constrained video coding scheme for mobile
multimedia players,
ICIP04(V: 2861-2864).
WWW Version.
0505
BibRef
Hill, R.,
Fung, J.,
Mann, S.,
A parallel mediated reality platform,
ICIP04(V: 2865-2868).
WWW Version.
0505
BibRef
Law, Y.L.[Yee L.],
Nguyen, T.Q.[Truong Q.],
Motion wavelet difference reduction (MWDR) video codec,
ICIP04(IV: 2303-2306).
WWW Version.
0505
BibRef
Marpe, D.,
Wiegand, T.,
A highly efficient multiplication-free binary arithmetic coder and its
application in video coding,
ICIP03(II: 263-266).
IEEE Abstract. IEEE Top Reference.
0312
BibRef
Chou, C.H.[Chun-Hsien],
Liu, K.C.[Kuo-Cheng],
Lin, P.Y.[Po-Yu],
A perceptually optimized and error-resilient video codec based on 3-d
sphit algorithm,
ICIP03(II: 787-790).
IEEE Abstract. IEEE Top Reference.
0312
BibRef
Berekovic, M.,
Flagel, S.,
Stolberg, H.J.,
Friebe, L.,
Moch, S.,
Kulaczewski, M.B.,
Pirsch, P.,
Hibrid-SoC: a multi-core architecture for image and video applications,
ICIP03(III: 101-104).
IEEE Abstract. IEEE Top Reference.
0312
BibRef
Sachs, D.G.,
Adve, S.V.,
Jones, D.L.,
Cross-layer adaptive video coding to reduce energy on general-purpose
processors,
ICIP03(III: 109-112).
IEEE Abstract. IEEE Top Reference.
0312
BibRef
Liu, L.C.[Li-Chang],
Chien, J.C.[Jong-Chih],
Chuang, H.Y.H.,
Li, C.C.,
A frame-level FSBM motion estimation architecture with large search
range,
AVSBS03(327-333).
IEEE Abstract. IEEE Top Reference.
0310
BibRef
Ong, K.K.[Keng-Khai],
Chang, W.H.[Wei-Hsin],
Tseng, Y.C.[Yi-Chen],
Lee, Y.S.[Yew-San],
Lee, C.Y.[Chen-Yi],
A high throughput low cost context-based adaptive arithmetic codec for
multiple standards,
ICIP02(I: 872-875).
IEEE Abstract. IEEE Top Reference.
0210
BibRef
Choi, Y.[Yunjung],
Cho, S.H.[Suk-Hee],
Lee, J.[Jinhwan],
Ahn, C.[Chieteuk],
Field-based stereoscopic video codec for multiple display methods,
ICIP02(II: 253-256).
IEEE Abstract. IEEE Top Reference.
0210
BibRef
Ali, W.,
van Zon, K.,
Optimizing a Random System of Cascaded Video Processing Modules by
Parallel Evolution Modeling,
ICIP01(I: 445-448).
IEEE Abstract. IEEE Top Reference.
0108
BibRef
Tsang, P.W.M.[Peter Wai Ming],
Lee, W.T.,
A novel interpolative codec for low bit rate applications,
ICIP96(I: 677-680).
WWW Version.
BibRef
9600
Zhang, K.[Kui],
Kittler, J.V.,
Using background memory for efficient video coding,
ICIP98(III: 944-947).
WWW Version.
9810
BibRef
Zhang, K.[Kui],
Bober, M.,
Kittler, J.V.,
A hybrid codec for very low bit rate video coding,
ICIP96(I: 641-644).
WWW Version.
BibRef
9600
Nguyen, T.,
Zakhor, A.,
Yelick, K.,
Performance Analysis of an H.263 Video Encoder for Viram,
ICIP00(Vol III: 98-101).
IEEE Abstract. IEEE Top Reference.
0008
BibRef
Lin, W.,
Tye, B.,
Ong, E.,
Xiong, C.,
Miki, T.[Toshio],
Hotani, S.[Sanae],
Systematic Analysis and Methodology of Real-time DSP Implementation for
Hybrid Video Coding,
ICIP99(III:847-851).
IEEE Abstract. IEEE Top Reference.
BibRef
9900
Chen, C.H.[Cheng-Hsien],
Lee, C.Y.[Chen-Yi],
A Cost-Effective Lighting Processor for 3D Graphics Application,
ICIP99(II:792-796).
IEEE Abstract. IEEE Top Reference.
BibRef
9900
Chen, J., and
Liu, K.,
A Fully Pipelined Parallel CORDIC Architecture for
Half-pel Motion Estimation,
ICIP97(II: 574-577).
WWW Version.
BibRef
9700
Cheng, S.C., and
Hang, H.M.,
The Impact of Rate Control Algorithms on Video Codec Hardware Design,
ICIP97(II: 807-810).
WWW Version.
BibRef
9700
Bergmann, N., and
Chung, Y.,
Video Compression on FPGA-Based Custom Computers,
ICIP97(I: 361-364).
WWW Version.
BibRef
9700
Mattavelli, M.,
Brunetton, S., and
Mlynek, D.,
Computational Graceful Degradation for Video Sequence Decoding,
ICIP97(I: 330-333).
WWW Version.
BibRef
9700
Ng, K.T.,
Chan, S.C.,
Ng, T.S.,
Buffer control algorithm for low bit-rate video compression,
ICIP96(I: 685-688).
WWW Version.
BibRef
9600
Boo, I.,
Arguello, F.,
Bruguera, J.D.,
Zapata, E.L.,
High performance VLSI architecture for the trellis coded quantization,
ICIP96(II: 995-998).
WWW Version.
9610
BibRef
Brahmbhatt, A.,
A VLSI architecture for real time code book generator and encoder of a
vector quantizer,
ICIP96(II: 991-994).
WWW Version.
9610
BibRef
Ruedi, P.F.,
Marchal, P.R.,
Arreguit, X.,
A mixed digital-analog SIMD chip tailored for image perception,
ICIP96(II: 1011-1014).
WWW Version.
9610
BibRef
Legat, J.D.,
Cornil, J.P.,
Macq, D.,
Verleysen, M.,
A real-time VLSI-based architecture for multi-motion estimation,
ICPR92(IV:147-150).
WWW Version.
9208
BibRef
Chapter on Filters, Image Processing, Restoration, Enhancement, Image and Video Coding continues in
Single Chip, Chipset for Coding .